Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/search/294727/?c%5Busers%5D=Fred+Chen&o=date&page=8
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Search results

  1. F

    TSMC Will Not Take Over Intel Operations

    Not sure if that has been defined clearly so far.
  2. F

    Updating our current logic density benchmarking methodologies

    It seems this formula has been around for years, but not necessarily followed (from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm): Going directly by the picture, it works out to 1.56 transistors/CPP/Cell height. It hasn't been followed by everyone obviously. One example is Wikichip...
  3. F

    Intel produced 30,000 wafers on ASML's high NA EUV

    If the "earlier" machines are the previous EUV NA, he might be talking about ~ 20 nm pitch. imec had just released some results for 20 nm pitch: https://www.imec-int.com/en/press/imec-demonstrates-electrical-yield-20nm-pitch-metal-lines-obtained-high-na-euv-single, still rough as expected...
  4. F

    Intel produced 30,000 wafers on ASML's high NA EUV

    It's likely (or hopefully) not used most of that time.
  5. F

    Intel produced 30,000 wafers on ASML's high NA EUV

    This should be a general new generation vs older generation thing. 3800 model should be similar improvement over older models.
  6. F

    ISSCC N2 and 18A has same SRAM Density.

    Looking at some prior but recent generations' SRAM design examples, of course they were frontside but they had Vss and Vdd lines on different metal layers. This is unlike the standard logic arrangement of both Vss and Vdd on same layer. I wonder if backside routing could not support so many...
  7. F

    ISSCC N2 and 18A has same SRAM Density.

    So Vss, Vdd connections for SRAM array are frontside, can't be backside?
  8. F

    ISSCC N2 and 18A has same SRAM Density.

    Yes, I saw that afterwards. Makes me wonder where else they would exclude PowerVia.
  9. F

    ISSCC N2 and 18A has same SRAM Density.

    I'm not saying it couldn't have been expected, just that it was odd to put this counter-spin to PowerVia at this time. I guess it means PowerVia will only be implemented in non-SRAM sections of the chip.
  10. F

    ISSCC N2 and 18A has same SRAM Density.

    Odd report: PowerVia didn't help bit cell density, made it worse in fact.
  11. F

    1b, 1c DRAM redesign by Samsung

    Samsung to increase next-generation DRAM 'chip size'... HBM Yield Improvement Priority Weigh in on yield stabilization instead of productivity... Earnings expected by the end of the second quarter Semiconductor Display Input:2025/02/10 17:05 Modified: 2025/02/11 10:09 Jang Kyung-yoon It is...
  12. F

    Why is Trump Targeting TSMC? Expert Reveals the Hidden Agenda: "Saving Intel"

    Intel started having the notorious yield issues at 14nm (before QP) so perhaps it is related to double patterning? They need to get that right, even when they have EUV.
  13. F

    TSMC Considers Running Intel’s US Factories After Trump Team Request

    Perhaps a better way would be to have potential US customers prepay the fab capacity.
  14. F

    China's top memory chip maker CXMT narrows tech gap with leaders Samsung, Hynix, Micron

    South China Morning Post January 30, 2025 ChangXin Memory Technologies (CXMT), China's leading producer of dynamic random access memory (DRAM) chips, has advanced its manufacturing technology to 16 nanometres, narrowing the gap with industry giants Samsung Electronics, SK Hynix and Micron...
  15. F

    China's SMIC Q4 profit slumps 38.4%, misses estimates despite revenue growth

    This seems to be mainly from mature-node (28 nm and higher) pricing for competition? Isn't their advanced process development officially stopped at 7nm (N+2)? They shouldn't be burning money there anymore(?)
  16. F

    Why is Trump Targeting TSMC? Expert Reveals the Hidden Agenda: "Saving Intel"

    A few days ago, I was just thinking how ridiculous this could get; I think that would be moving TSMC's Taiwan fabs.
  17. F

    TSMC Considers Running Intel’s US Factories After Trump Team Request

    One way to frame it could be Intel licensing to TSMC. It is not Taiwan taking business away from US. Intel Foundry has its chance now. It's all the customers' choice.
  18. F

    Why is Trump Targeting TSMC? Expert Reveals the Hidden Agenda: "Saving Intel"

    "No customers"? That hasn't been reported yet. But the splitting of Intel has gotten much news this weekend for sure.
Back
Top