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Ailing chip giant targets 2027 break-even as costly EUV tools raise stakes
Dan Robinson
Wed 14 May 2025 // 17:20 UTC
Intel is wooing external chip customers for its 14A process node to justify the high costs involved, and aims for the foundry division to break even by 2027 - as part of ongoing...
I don't know that it has been proven in volumes anywhere close to production yet. Of course, a limiting factor is that it only fits regular grids of features, so maybe some DRAM layers may be immediately relevant for now. Actually, I had the impression Intel had dabbled with it, not sure where...
A large part of it is also the NA made a big jump this time (67%), which is different from prior generations (10-20%). Depth of focus dropped a lot. Resist is supposed to be thinner than it, so it will be too thin (<30 nm).
The wavelength jump can also be said to be too drastic, becoming...
Nvidia’s decision to establish its international headquarters in Taiwan is expected to bolster its China export strategy, according to industry analysts.
The move, announced during CEO Jensen Huang’s keynote at Computex 2025, positions Taiwan as a critical hub for Nvidia’s AI and semiconductor...
The secondary electrons from below the resist are obviously a very random, stochastic input image source in addition to the EUV input. But the image inputs do not stop there. The plasma environment above the resist generates plenty of exposing non-EUV, non-confined energy (VUV, electrons...
During the EUV lithography process, a significant fraction of EUV photons is absorbed by the underlayer (UL), potentially leading to the emission of electrons that can alter the chemistry of the overlying resist. In this study, we address the challenge of understanding how such electrons...
TAIPEI (Taiwan News) — Nvidia CEO Jensen Huang (黃仁勳) announced Monday at Comptex that the company’s new overseas headquarters will be built in Taipei’s Beitou-Shilin area, ending months of speculation and signaling a major expansion in Taiwan.
Dubbed “Nvidia Constellation,” the new office is...
As the semiconductor process further scales down to 2nm and beyond, the multi-patterning technology has emerged as the clear choice of the routing metal layers even within the era of extreme ultraviolet (EUV) lithography.
The stitching technique within multi-patterning can divide a node into...
I know the guy, he's an intense history buff (Asianometry channel covers many interesting historical episodes, not just technological).
But in the complete picture, it isn't enough to only consider the response of the resist to the EUV radiation. You also have to consider the EUV-induced...
Yes, I remember seeing the same report, a D0 of 1.5 would give 30% yield for a 9 mm x 9 mm chiplet.
But this is for an SRAM macro. It might be different for other chips: https://www.digitimes.com/news/a20250325PD228/tsmc-2nm-fab-yield-rate-2025.html
I've always felt EUV R&D should be more exhaustive before implementing in high volume. The amount of R&D wafers needed could be or should be millions.
The list of questions practically has no end.
Here we have undesired exposure to EUV-induced plasma electrons from different exposed fields...
