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If you count IMS as "big", I think that was pretty reasonable. It started as an investment so IMS could afford to develop their multibeam writers in 2009 with intel buying the rest of the shares in 2015. Now it is valued at $4.3B, unfortunately I can't find how much intel paid for it. Maybe it...
Intel was the process leader in the early xRAM industry as well. I guess they also invested EPROMs (but I am not old enough to know how significant that is/was). What I do know was a big deal is that intel was the initial firm to take the leap from bipolar to MOS.
Very true. Although I guess it...
I hate to break it to you, but EVERY processes technology since the dawn of man has a V-f curve that falls off a cliff at high voltage. This isn't a TSMC exclusive phonemina look at any chip ever made. You will see the same thing. See the last page for why ARL actually has a lower Fmax...
There's no point to develop the process if intel isn't getting paid a lion's ransom in royalties for all of their upfront investment. If the licencing fees are that high, then I suspect others have no incentive to build EUV capable fabs because the payback period is way too far in the future to...
Old IEDM/VLSI papers can be found on IEEE and go through many of the characteristics that process engineers will pour over (Ion, Ioff, DIBL, SS, etc). The closest you can get to an "all encompassing" performance number for a node would be ring oscillator frequency. It doesn't give you the whole...
People need to stop with this notion that process performance = Fmax. This has never been true even in the Dennard days. Fmax is a product dependent criteria. Power = Cdyn*V^2*f + leakage. ARL will have inevitably higher power consumption floor from cross die communications and the IOs/uncore...
I hate that choice, terrible choice. I can think of 6 names off the top of my head that are actually worthy successors. Now maybe what they meant as the CTO of mother Intel, in which case sure knock yourselves out. What I do know is that Intel chip designers shouldn't be allowed to step anywhere...
Maybe I am not creative enough, but if you are doing the BCN fully from the FS of the wafer, I assume the flow goes something like: CFET FEOL -> finish bottom device FEOL -> bottom device MEOL -> finish top device FEOL -> top device MEOL. If you do the BCN from the BS you can do: complete FEOL...
By your logic N3 yield is terrible because LNL and ARL both have smaller die sizes, slower ramps, and clock lower than RPL. And we ALL know N3 yield is NOT terrible. Clock speed is more heavily influenced by design than process (see ARL having a large clock speed regression vs RPL despite being...
My understanding is that SRAM also tends to have a lower DD than logic at iso process health due to the higher uniformity of an array vs random logic. But with GAA maybe this isn't the case because HDC SRAM would be using minimum Z nanosheet which are the most suspectable to the high LER from...
Your statement indicates you have never worked at a development fab or talked with folks who have worked at multiple firm's TD sites. Just about everything in this post is incorrect or against industry standard practices, but I will leave it at that.
Just from public information and how TSMC'S...
18A wasn't on the roadmap back then. The 5N4Y in July 2021 was 10nm SF, i7, i4, i3, and 20A. Dollars to donuts if 18A was announced back then that slide would have said 18A. Granted we are being pedantic because 20A and 18A are the same base node and the names are completely arbitrary.
I can’t think of a more fitting name for a fab in Minnesota. Don’t know why there are so many random semi firms up there (such as TELs surface treatment and IBE tool development and manufacturing as well as Skywater), but I’m here for it.
I wonder if TSMC employees a corps of compressed work week module engineers in addition to the normal tool owners and 855 module engineers? My experience is that having dedicated night and day shift engineers is a 10x improvement in work-life balance. I think there are some costs in that 855...
Because TSMC passes only a trivial amount of the wafer cost savings as a node ramps to full production and as deprecation expenses go down. In their earnings TSMC for the past few quarters has said N3 drags down their corporate margins (which is normal as this happens with EVERY new process)...
Ecosystem folks like EDA, arm, etc are easy choices for a board. But I would assume it would be hard to get customers on the board. While I think it would be super sick to get Jensen, Cristiano, and Rick Tsai (doubly so from his time at TSMC) on the board, I am skeptical they would want to do...
Incorrect Dan. Intel 4 does have IOs. Even if you want to ignore the high speed D2D connections on MTL cpu die, FIVIR, PLLs, etc. The edge version of Xeon 6 has full ethernet and PCIE interfaces on an i4 IO die. Heck if you look at older intel roadmaps large die Xeon 6 was listed as intel 4 not...
How so? i10nm was originally supposed to come out in 2016. Since 14nm was like 6-9mo late and with a slow initial yield ramp, if you want to be generous to intel maybe you will cut them slack and say 10nm should have come out by 2017. Real HVM for 10nm started in 2019 and icelake feels like it...
The number is meaningless without know what it was. If the product in question was Exynos W1000, then I flat out don't believe the process is that bad. DD would need to be OVER 11 with a die that tiny to be sitting at 20% die yield. Even 9% yield would be at 17.7 DD. The TEMs may have looked...
