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What expectation was incorrectly set? Intel said they want to use it with 14A with plans to do a proof of concept/derisk on 18A, and that they would only fully commit to it when when the maturity is sufficient for Intel to start use it for HVM.
Process development and customer qualification...
This is a common misunderstanding. Putting aside the transistor variation/process maturity part of the equation limiting frequency, SRAM Vmin, etc. There are two major issues. One as you mentioned was the growing problem of rising interconnect RC slowing down chips. The other is that in a post...
I never said N2 didn't have tape outs, but tape outs don't equal HVM. If they did, then we could say absurd things like N3 entered HVM one year after N5 HVM (in 2021). TSMC even went so far to say the first production wafers won't ship to customers for revenue until late Q1 to early Q2 2026. How...
A little early for an April 1st joke news.mydrivers.com. N2 isn't supposed to enter HVM until the very end of the year (TSMC's own words). If Apple was actually going to use N2 for this year (especially for the non pro) TSMC would have needed to have started HVM back in December or maybe at the...
Yes
Yes. Even if it is "only" 44W for one core there are thermal concerns. Even though 44W isn't a ton of heat in the area of one core it is an absurd amount. I am sure you aware of the concern of thermal runaway and how this is why thermal throttling exists. Just because the rest of the chip...
There is no such thing as a scenario that isn't power constrained. For example; that 14900KS does hit a power and thermal density limit. Use some Liquid N2 and you can go faster. But even then, at the end of the day you hit a thermal wall. Power and performance are two sides of the same coin...
I don't have reference papers, and I am dry etch rather than wet etch, so the following suggestions will obviously be colored by that. Assuming your etch byproduct isn't just some particles of etch polymer (because if it was, I would try cyrokinetic cleaning); I would try a plasma dry-clean...
Public evidence of culture change include various recent papers Intel has shown that include tidbits about various changes to their development model and how they do development vehicles, and crediting these changes with increasing the rate of learning. There is also the public proof point of...
Interesting the advanced packaging fab seems to be at Austin rather than Taylor (assuming that Samsung still plans to do advanced packaging in Texas and that this is what the Austin expansion is about). Because Samsung hasn't expanded Austin for the better part of two decades I figured they had...
I think that is valid. However, to be fair, the situation is far different from it was. Back then, Intel's TD org was running on an insufficient R&D budget to keep pace with a TSMC or a Samsung (although Samsung is hard to say since we don't know what the TD wafer split is between memory and...
I've seen this claim before, and it makes actually no sense. That is not how anything works.
1) 20A "with the 18A" libraries is just 18A. They are the same bloody process, and I can't understand for the life of me why this fact eludes so many people? Per intel, 18A is 20A with some performance...
The chart is a little weird. So the IO line is the cost per FET of a 16/14 "nm" class node with 11 metal layers. I would assume that drop is likely just wafer prices coming down. Some of the declines will be from different defect modes being squashed over time, and others might be as the...
Your good Xebec, I wasn't calling you out and I know it is OT. I just see statements like that quoted all the time and wanted to nip it in the bud. Fab engineer who works at 28nm and below fabs could tell you it just isn't true. Densities have simply increased faster than the cost adder. Only...
I've said it before, and I will say it again. Jensen is full of baloney on this. Even a process that is comically overcomplicated for its density like intel 7 has a better cost per FET than intel 14nm (albeit not better than a usual full node of scaling like intel guided back in the 2010s if one...
UMC post exiting the leading edge. But Taiwanese companies have strong chairmans (unlike most modern American companies) to act as something of a tie breaker. Technology development and manufacturing is under SC Chien and customer engagement/design enablement and strategy are under Jason Wang...
I feel like this is the root of Intel's problem. Just commit to a damn strategy. Does the board want fab-lite (and presumably soon to become fabless due to how awful leading edge development is while fab-lite) Intel (Bob), or does it want fab-strong Intel (Pat). You can't keep flip flopping...
Maybe I didn't understand what you meant, but wasn't that always a given regardless of implementation? Similar to making the statement that a transistor's contacts need to be aligned to the transistor and not shorting to the wrong terminal or the wrong transistor.
