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Samsung is in the middle of a prolonged commodity memory downturn, a crumbling embedded business, and image sensors and Exynos got booted out of both Chinese and many of Samsung's own phones. So that obscures the situation, since Samsung's financials are far more opaque. They also missed the...
Faster than Ireland with Intel 4. Per Intel, they didn't start running the first full loop qualification material in Fab 34 until August 2023. Seems consistent with talk of much greater wafer requirements on 18A vs i4 (at least early on in the product lifecycle). Although Pantherlake needing...
Considering native Chinese DUV systems have a lower field size than industry standard, and worse throughout and overlay than a Nikon. I smell a wiff over of optimism in the air. I wonder if relying on complex multi paterning schemes with more sophisticated imported tools is better than simpler...
I wouldn't exactly call Intel chipsets niche or low volume, but that is probably a reasonable charcterization of a lot of the Austin customers beyond Intel after Qualcomm, Apple, and NVIDIA moved to more advanced Samsung and TSMC processes.
Funny to think that after Qualcomm abandoned ship...
Are you talking about self cleans of the clean room or in-situ chamber self cleans (the terminology we are used to might be different)? In my personal experience the former seems like it would be of little value given how infrequently defects I have seen came from outside the chamber or Mom...
To be fair that was before internal wafer requirements cratered for the second time. It was also before various initiatives to get more capital efficient (although some amount of that was probably assumed in DZ's model on incomplete data from the new accounting). After all Intel originally...
If that was BS's strategy he would have done it rather than wasting money on things that had no place in his vision of intel. With that said what Pat suggested would have been the obvious end result of that "strategy". After all what is the point of building fabs and developing process...
Intel is commonly believed to have had more scale on 10nm than TSMC had on N5 back in 2021. Even the most conservative tecinsights estimates had the Intel 10nm factory network at well over a million wafers per year at peak ramp. There is no indication that scale was ever a problem at that time...
Looking through the website I found this. Seems like it might be low volume though if they used the term select customers and universities. Not sure if TSMC and Samsung have a broader MPW program.
As an unrelated note on the IF website they claim 9 publicly announced 18A customer wins. With...
I really don't get it. Wafer costs can be kept similar at same or better density, or density can be dramatically better if you are willing to increase wafer cost. And not wanting to move to different metallization schemes down the line WILL cause power-performance inversions vs prior nodes. It...
My point was that over 15 fabs were needed just for Intel with simpler purposes technologies back in 2022. From 2022-2030 Intel announced plans to fully ramp 9 fabs. Granted these fabs were bigger than the average across Intel's pre EUV fabs. But they need to be bigger to support bigger tools...
Yes back when Intel products had a larger wafer demand than Apple pre 2022. 15 fabs of 10/14/22nm and Intel still couldn't keep up with demand even outsourcing chipsets to Samsung for 12th gen.
Partially it is. Outsourcing started because Intel's factory network was too small to handle all of...
Zen CPUs don't use advanced packaging. It is basic organic MCM. Any major OSAT can fulfill the simple requirements for organic MCM. Intel has been doing it for decades with graphics, chipsets, memory, and SRAM. Others have done it too IBM etc. Funnily enough Intel fab'd advanced packages before...
TSMC said that 4.2 GHz speed was for the HC array not the HD array. The major difference between Intel and TSMC methodologies seems to be the different operating temperatures for the testing. Also from what I have seen SRAM performance and efficiency is not 1:1 with logic, so I am not taking...
+1 for how things were in the past. I think the most foolish part was doing crazy overtime just to make that human glue, and then taking pride in this clearly unsustainable way to do things. I think there are other angles at play, mostly related to penny-pinching choices that set LTD up for long...
Did you mean a lot or a wafer? Perfect wafers in my experience aren't too rare on a 4+ year old process. For a whole 25w lot, yeah that is pretty hard. I bet it isn't too hard to find a passive interposer lot that is perfect though. They are comically simple and perfect wafers are almost an...
I assume the article writer butchered the order of words and that they meant that 18A would be used to develop high-NA. This would be consistent with prior statements from Ann Kehleher and Mark Phillips that high-NA would be debugged on 18A. This could be like TSMC debugging immersion on 90nm...
I don't think so? But my understanding is a bit shaky. My understanding was that for a 6T SRAM the Vdds and Vss just connect transistors within the bitcell, right? I thought that all electricity into and out of the bitcell flowed through the BL and WL. If that is the case, then only the bitcells...
Nothing else comes to mind, but SRAM didn't come to mind to me until I saw it... Logic only sees benefits and unlike the SRAM bitcells inside the array has power rails that can be deleted to save space. So I have to assume all logic cells will have it. I guess passives/some analog devices might...
Fair... Although with the technologies speaking for themselves/already demonstrated (behind closed doors and at conferences). It isn't like Intel needs to hide that information for an industry white paper. While armchair experts might quibble about is BSPDN worth it. The actual logic players all...
