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I feel like Samsung should have started A10 development sooner than this. TSMC said they were extending development times to 5-7 years, and even back in 2008 when things were simpler, Intel said they started full process development 4 years before products came to market. Even if we are talking...
Bad business call. If I was TSMC I would be doing everything possible to be fighting tooth and nail to win every Intel design I could. Even something as simple as getting the U series PCH is more wafers than all of AMD. Think about it like this, Intel products even after having their sales...
I'm surprised. AMD was always slower moving to new TSMC nodes. Launching N2 products in 2026 alongside first Apple products is a big shift. And a welcome one, because I feel like their old strategy of not using TSMC's best was a disadvantaged strategy.
No disagreements here.
You say that as if most Intel process technologies didn't have exceptional DD by product PRQ. The organization and systems did rot over the years, but the talent really did human glue some miracles until complexity and chronic underinvestment made the tasks too large to...
I acknowledge that. But at this point (2025), that isn't as big of a problem as it was say 10 years ago. 8" GaN and SiC have been in HVM for a little while now and based on the rapid progress from various papers I have seen, 12" GaN is literally on the cusp of commercialization. Now granted I...
No it isn't. TI is an IDM and has FAT margins (like TSMC margins level good and WAY higher than peer firms like UMC tower or GF). Meanwhile the few fabless equivalents to TI and STM practically strugle to pull in single digit margins! As long as you can FtF! (Fill the Fabs!) IDM has always and...
"HPC" in the foundry world is everything bigger than a smartphone (like 5-8W). In fact, if you look at how TSMC and UMC used to talk about things (and how UMC still talks about things), even smartphones were lumped into the HPC category back when foundries were mostly doing puny little low power...
Sunny is an academic institution D1 is a commercial facility. I also doubt Intel wants academics poking around their fabs. The US Senate leader at the time was also from NY. So that certainly couldn't hurt NY's case. The only benefit to building a brand new facility from scratch in OR (since I...
Intel products isn't exactly well known for their stellar customer focus. But AMD seems worse in this regard. CCG worked with OEMs to develop technologies for new categories and has done work to level up OEMs to make the newish so--called "macbook compete" class of laptops. AMD seems to have a...
That isn't how BSPD works. It isn't advanced packaging. BSPDN is part of the wafer making process not the packaging process even though the underlying technologies are somewhat similar and employ some related manufacturing techniques. NM is for advanced packaging not 18A.
TSMC has to enter risk production sooner because they need to transfer process to HVM fab before HVM while Intel does HVM at the development site. And foundry customers will want a new product qual at the HVM site no matter how closely matched the HVM site is to the development site to minimize...
The problem with SAC is etch. If you do your gate cut after RMG your etch needs to eat W but the contacts are also W. And the whole reason TSMC went with SAC was it was getting to hard to place the contacts lithograpically. If you wanted to try an etch mask over the contacts to protect them...
The only pitch reductions were at M1 going from 30nm -> 48nm and the CCP going from 47nm (optical bloat from the originally published 45nm) -> 48nm. On N5/N3E TSMC does poly cut after RMG and uses EUV to direct print their contacts. With N3 and the 45nm gate pitch TSMC came to the conclusion...
That wasn't the main cost savings. The biggest cost savings and long term yield enhancement from N3 -> N3E is getting rid of that Self Aligned Gate End Cap and moving from self-aligned contracts to direct print contacts. Things like moving M1P from 3:2 CPP gear ratio to 1:1 and using direct...
LNL is hilariously more efficient than ARL in the intended scenarios for LNL:
On package memory
IMC on compute die
Fewer D2D power losses
Higher percentage of total Si area using the most advanced process
Better NPU and GPU IPs are more efficient
Smaller GPU (more power efficient)
GPU, NPU, LP...
You have in a sense. When TSMC says hey when all is said and done this Fab will cost us x NTD. That is effectively a sum of lifetime deal values across construction and tool vendors. When ASML talks about their current order book for x type of scanner being however many billion dollars, that is...
I don't see how that sounds like a bad product? LNL is about as good as it gets from non Apple PC battery life. Scaling lunar lake like efficiency to ARL performance for high TDP skus and bringing LNL battery life to cheaper segments and offering better margins in the segments Intel already put...
What would the alternative be? Let Ireland sit idle, have D1 run Intel 3 until the end of time, and then have insufficient floor space to build a solid development/pilot line so future nodes can be developed? BK and BS tried that "strategy" and the consequences are shown clear as day on Intel's...
I doubt Taiwan would be jazzed about their baby becoming the underling of a GF. There is also the little detail that GF is already foreign owned and the US hasn't put any pressure towards changing that.
No: they don't. Samsung has a solid finFET node that GF licences and an SOI finFET process...
Why would GF be in charge? If anything they would be last in line. UMC is the better foundry company, and if we want to entertain the less likely idea of Intel selling their manufacturing arm to the combined entity; Intel foundry has more scale than both of them combined and would also be the...
