You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Intel has by my count over the past 2 years announced 7 signed wafer agreements for 18A. In 2023 two unamed defense related ones and one unamed customer who in their contract will at some point pay out Intel a prepay for their capacity. In 2024 Microsoft AI chip, Amazon AI fabric chip, and in...
https://www.intel.com/content/www/us/en/foundry/process.html
Why? It takes years to go from signing a wafer agreement to being mostly done with the design and tapping in your A0 step. Just over one year ago Microsoft said they recently started work to design an AI ASIC for 18A. It isn't a...
Intel has time and again talked about how the design ecosystem, PDK, EDA, IP, and design ease of use where never intended for foundry on Intel 3, because they started development YEARS before foundry was even an idea in anybody's head. Heck just last week they were mentioning all of the hardship...
Depends on how you mean. Assuming that we are talking revenue, and we aren't talking about maybe Intel consistently out-executing TSMC for the next 20-30 years. Then TSMC needs to have at least 3 10 nanometers in a row. The most recent 2 TSMC nodes have for the past little while have been around...
Obviously I wasn't the one who made the decisions. So I can only offer an educated guess. I would lean towards it being because A16 FS interconnects and the devices are the same as the N2 ones. Same fab same equipment. So unless high-NA was ready for HVM in late 2024 (just in time for the N2...
Each metal line is a "track", not just M2 lines. Scotten likes to look at up to M2 since you go up to that level to make more complex logic cells and because beyond M2 my understanding is designers are more so looking about block routing rather than individual cells. Simpler cells can be done...
For the previously mentioned reasons from my earlier reply about it, that would be my assumption. Could be wrong, though.
Fair enough. Humor in text form is certainly harder to understand.
Apparently Kevin Zhang said it inside this interview linked in this post. This awful internet journalist...
The chart looks even wonkier with HP libs. Using the VLSI cover photo Intel's M0P on 18A HP is 36nm rather than 32nm (18A HP presumed same size as 20A based on i3 HP being same size as i4) than HD, and because 18A HP is significantly denser than N3E HP (upwards of 20%). Don't have N2 HP data...
I think I understand what you are trying to get at, but why present it in this way? None of these processes use 6 M0 tracks (other than N7 and N2), and metal track reduction has been a key method of delivering density improvements in the late 2010s/early 2020s. I feel like a better plot to show...
I'm shocked you thought I was in marketing for these nearly 3 years. Not a dig at marketing people, but I figured the content of my posts and prior comments about my experiences in dry etch, process integration, and in semiconductor manufacturing kind of precluded me from being anything other...
My experience is obviously colored by my experience with leading edge process R&D but I feel that verbage is far too dramatic and sensational for something so routine in manufacturing and in R&D.
Having fallbacks is objectively good. It makes delays less likely because you aren't burning the...
Intel story has stayed consistent on this point.
Pat said the same story as Ann.
They never said that. What they said is they have both with low-NA as a fallback option and that the processes are transparent to designers so Intel can use whatever is best. IMO Intel calling it out again is...
I think your overthinking this Dan. high-NA looks to be ready for some kind of insertion in time for 14A. 14A development started before Intel even got their first tool so there needed to be a lowNA version. high-NA comes and Intel says they are happy with the results and continue to say they...
They have mentioned it on earnings a couple of times when folks were concerned about risk. I think when Ian Curtis interviewed Pat last year Pat mention it. I think Intel discussed it at last SPIE. Lastly they also showed off a completed 14A wafer with test chips last direct connect (which was...
I guess it could be 1 EUV backbone with pitch doubling plus 2 block masks, or SALELE with one block mask? Considering 18A MMP is at 7nm class levels, one would assume 14A is around 5nm class levels due to the modest density uplift over 18A. So I guess those schemes seem plausible.
What is weird...
Ah I see what you mean now.
Litho doesn't give PPA though. Anything I can do with highNA I can after all do with a Hg arc lamp and A LOT of pitch division. It just won't be cheap or high yield. So if Intel thinks highNA is right for them then it has to be because area cost or design ease of use...
So pitch is a function of feature size and distance between. Is that focus issue a problem when it is same line width but wider spacing? What about the wider line width identical space between scenario?
Unrelated but...
Funny quirk of GAA. I wonder if the HP cell will be even non Intel...
Just talking 18A: Microsoft said last year they were signed on to use it. As did Amazon, and according to their website apparently 7 other people signed on (if you also count the USG stuff). Supposedly double-digit adv packaging design wins. Mediatek on i16 for digital TV and WIFI, and a...
