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Yes and no.
So the diagrams intel has shown show the powervia coming up inside the cell boundary region and then the TCNs extending over the top of the boundary region to land on the powerVIA. Since this is below the metal routing layers it does not minimize the benefits I had mentioned about...
Yeah, I can add some color to my statement. TSMC said SPR is optional on A16 and that N2 IPs are drop in compatible. This indicates that A16 uses standard cells with the same size as N2, and that the M0/M2 power rails are still there (hence preventing any compaction of the cell height). It is...
Shockingly, intel and TSMC seem to have shockingly consistent messaging on the matter:
TSMC's comment that N3P wouldn't be better than 18A, but that N2 would definitely would be the "most advanced process when it comes out"...
I highly doubt the toolset for A16 or even N2 will be basically the same as N5. There are many parts in a GAA and BSPD process flow that have no finFET analog. The only things that will likely be very similar to the point of interchangeability is many of the BEOL segments between N3/N3E/N2/FS...
Okay we are on the same page, and good catch on Spanson. I forgot that they weren't bankrupt/absorbed by Cyprus semi yet.
As for the IBM allience, FWIW Samsung dumped the IBM finFET process and the IBM HKMG process for their own internally developed processes and GF would use Samsung's finFET...
This was at a press event with the objective to talk about how super dupper awesome intel's technology is. It is hardly surprising this was a narrative that intel would tell their engineers to bandy around. Not really any different from the mudslinging that TSMC or Samsung rattle around to...
At the meeting where Intel explained the new accounting model, Intel claims that Intel foundry is less than 1/3 of the total head count. So being and IDM has very little to do with Intel's bloat. Now should Intel foundry have around half the headcount of TSMC while having like a fifth the...
You never know but I would place it in the unlikely category. The chip level density improvement is too anemic for it to be likely. If there was a pitch shrink (and the resultant cost and cycle time increase) plus all of the extra processing steps for GAA then the cost per wafer cost increase...
The SRAM macro shrinking is not super surprising since TSMC is always good about finding clever design tricks to get more density, but the bitcell size shrink in spite of the suspected lack of CD shrink is more so. I have only seen the bitcell number in the Tom's article. Is that bitcell value...
https://semiwiki.com/forum/index.php?threads/intel-shares-jump-despite-massive-loss-as-chipmaker-touts-%E2%80%98solid-progress%E2%80%99-cutting-costs.21366/post-76926
I already said the choice to not use intel 7 was made while intel fabs were overloaded and CCG thought they would stay that way...
By TSMC's metric of at least a 2% PPA improvement counting as a node, TSMC has done 6N4Y (N5P, N4, N4P, N3B, N3E, N3P) during the same period of intel's 5N4Y. By Intel's metric of anything with a greater than 10% PPA improvement counting as a node, TSMC has done 3N4Y (N5 -> N4P, N4P -> N3B, and...
Yes Intel says they use SAPQ for those nodes. At VLSI intel said the main application of EUV in the BEOL was for greatly simplifying blocks/cuts, via patterning, and the medium pitch metal layers. 30nm M0 is also too tight to comfortably do EUV direct print. So Intel would either need to do EUV...
^ this is your answer for how intel keeps intel 3 around for the long haul. i4 is basically just i3-early and 20A was basically just 18A-early to steal terminology from Samsung, or the equivalent of N5 (Apple and Huawei before they got sanctioned only) vs N5P (what everyone inclusive of Apple...
That wasn't a co-development situation like with UMC. That was just running as a second source capacity upside for Tower 65nm. Also, that was in Fab 11/11X in NM which never ran an intel logic technology past 32nm. Funnily enough, they even have it on their website as if it is their fab, which...
Intel did literally say that. Even just logically this should be obvious. Good example is M0 patterning. On Intel 7 that is 40nm (if memory serves) and done with spacer based pitch division. Okay sounds doable with dry DUV (160nm core feature) and with way more etch, dep, polish, and metrology...
Yes, but I think you greatly underappreciate just how much volume Intel runs. For one Intel said they want to convert F42 to 18A, so that equipment is no longer needed. Nor would D1's Intel 7 line serve any use going forward. Israel also runs Intel 7. Techinsights estimates put Intel 7 peak ramp...
That's easy. The ghost of Christmas past is haunting Micron. They are the smallest major DRAM and smallest major flash manufacturers. The memory industry is all about running flat out and maximizing economics of scale. The cost per bit advantage of say 1-alpha to 1-beta is much smaller than say...
He also calls SK, Kioxia, Micron, and other IDMs as "foundries". So I assume he is counting memory. Stupidity aside, I highly doubt TSMC has more wafer starts than Samsung (if you include memory). Samsung has a larger share of memory than TSMC has in logic and there are more memory chips/CMOS...
