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I think Daniel Payne is right about where Intel fab info does NOT come from (vendors). I recall the info about litho problems with the aggressive shrink came from an actual Intel disclosure 4+ years ago. Ditto for Cobalt.
EUV could have been earlier if they had not decreased funding for it at a critical stage in its development in 2005. They had just developed 193i with a researcher at RIT, as I recall
Rumors do trickle out of a fab, esp since vendors are in the fab trying to improve the equipment/process that is "causing" the problem. Even a bystander in the fab can see where all the effort is going when there is a yield problem.
Does anyone know the cause of poor yields? I have heard Cobalt or lining of Cobalt or Quad Patterning. If it's Quad, they should have moved to EUV earlier, but then again I am biased toward EUV.
Early on Intel said they tried to do too big a "shrink" in dimensions, jumping one 1 1/2 or 2 nodes...
