You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
This is a surprisingly complex subject.
I remember back in the late nineties at the Advanced Semiconductor Manufacturing Conference there was a lot of talk about the Theory of Constraints and everyone was reading "The Goal" by Eliyahu M. Goldratt. There was at least one company who designed a...
HKMG is used in the periphery for high performance DRAM. Samsung started making DRAM with and without HKMG beginning at 1x, Micron at 1z and SK Hynix at 1a. Samsung 1x is 7 years old, HKMG isn't that recent an addition. It is only used when needed for performance due to the cost sensitivity of DRAM.
I took that same course at IEDM, I also know Paul pretty well. With all due respect to Paul, a few comments.
"As I'm sure you have heard, simple dimensional scaling (aka Moore's Law) is running out of steam, and DTCO approaches are required to keep scaling on track."
What Gordon Moore...
Imec developed an incredibly dense vertical FET (VFET) SRAM with a relatively simple process flow years ago and my understanding is no one is interested in it. As far as I can tell none of the leading edge logic companies are working on vertical FETs. When I first saw it I thought it would be a...
GLOBALFOUNDRIES 7nm paper at IEDM 2017 was 6 tracks as I wrote about here: https://semiwiki.com/semiconductor-manufacturers/intel/7191-iedm-2017-intel-versus-globalfoundries-at-the-leading-edge/
I don't completely understand it myself, I will touch base with someone I know at Imec. I thought I had a general idea but I am not so sure now. By the way, what is GF7?
I don't have specific numbers for 8nm, I just picked that because it is the last generation before EUV at the foundries. The key point to me is resistance was always an issue but a manageable one and it wasn't until recently that it became such a problem that people started looking at solutions...
It depends on what you make and who your customers are. Foundries need shorter cycle times to respond to changing market conditions. If you are making diodes you might not care about cycle time and just load up the fab. If you are early in the yield curve for memory you also need short cycle...
With respect to HNS, they are a natural evolution from FinFETs with 85-90% of the process steps in common. HNS have better electrostatic control than FinFETs and gets you about 3nm in Lg resulting in smaller CPP. They also provide better Weff per unit of horizontal area.
Once you are into HNS...
The benefits don't justify the cost and complexity.
If we define "DUV" processes as 8nm and above, Backside power delivery (BSPD) solves two problems at the leading edge that don't exist for "DUV":
1) BSPD can reduce the width of the cell boundary enabling 5 track or shorter cell height, but...
Why do you think VFET is a pre-requisite for monolithic 3D, monolithic CFETs with HNS have already been demonstrated and I personally know of work being done or more than 2 layers.
For a given node the cost to run wafers goes down by more than a half over the first five years. Initially ramping up and improving yield, eventually equipment becomes fully depreciated and that is a huge cost drop. Labor costs generally drift up and most material costs drift down, although...
My understanding is FinFETs can get to 5 tracks without BPR or backside power delivery, HNS need BPR or backside power delivery to get to 5 tracks. Forksheets can get HNS to around 4.3 tracks and there are some other routing tricks that can get HNS to 4 tracks. CFET can get below 4 tracks.
It depends on the process flow, exposure tools run >250 wph, CMP 60 to 80 wph, implant can be up to 500 wph for some tools, etch varies a lot, for example 3D NAND channel etches can be an hour per wafer. I plotted throughput by tool type for a whole variety of processes once and the data points...
By the way, I say horizontal nano sheets (HNS) because GAA is a more generic term, in fact VFETs if ever used will likely be GAA as well. I don’t think we will see VFETs because they don’t have the long incremental scaling path that HNS do.
