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Take EUV, even with uptime <90% it was adopted because it was essential for continued scaling. Getting above 90% and ultimately approaching 95% required new/upgraded versions.
This is a longer conversation than I have time for but simply put....
The technology needs outweigh the manufacturing needs and the technology is harder than any other manufacturing processes on the planet. You have incredibly expensive tools that are immature and therefore are down a lot...
It not speculation on my part. Samsung has cleanrooms on two floors in many if not most of their "fabs", there is often a NAND Cleanroom and a DRAM cleanroom. In Pyeongtaek there is P1 with two floors of cleanrooms with NAND and DRAM, P2 has 2 floors of cleanrooms with NAND, DRAM and Logic, P3...
I know it for a fact, if I am posting a rumor or speculation I say so. A lot of these fab have a floor running NAND and a floor running DRAM, some fabs have a mix of DRAM, NAND and Logic between the two floors.
Some of it is building code related, in the US it is hard to design a single level cleanroom that meets the building codes, in Korea Samsung builds multi story buildings with 2 of the levels used as cleanrooms. At least some of their fab buildings are 8 stories tall, that isn't allowed in the...
That is YMTC's buzz word for it, Kioxia calls it CMOS directly bonded to the array (CBA), Samsung will likely have a different name for it when they adopt it. The marketing guys have to earn their pay.
Stress management is a huge problem and also the yield is better. Not having the memory stack over logic makes stress management easier. Samsung showed it on their roadmap at IEDM a couple year ago. My belief is as we get above 500 layers everyone will go that way.
There are multiple approaches to 3D DRAM but the one getting the most attention at the device manufacturers has a stack of layers that are all patterned together. There is an approach where each layer is patterned and then they are bonded together but it is unlikely to be cost effective.
I think it will help Micron and Samsung on the DRAM side because it will constrain what SK Hynix can do in China and SK Hynix is also encountering long delays in their Yongin fab complex. Micron is planning new Fabs in the US but currently the majority of their memory is made in Asia.
Per Digitimes Asia "Samsung, SK Hynix might not be able to produce next-gen memory in China in 3-5 years, warns expert".
I find this pretty funny, SK Hynix has a big DRAM plant in China. SK Hynix has already ramped up their 1a DRAM outside of China using EUV, their inability to utilize EUV in...
Optimizing Factory Performance by Ignizio is a pretty good book but not semiconductor specific and I have seen comments from him that show he doesn't understand the unique aspect of semiconductor manufacturing.
"for example: if litho machines are $120M each and etch machines are $10M each and you get approximately the same cycle-time/throughput behavior from 4 litho tools + 20 etch tools = $680M, or 5 litho tools + 12 etch tools = $720M, then you're going to pick the $680M case."
I don't think that...
There are essentially no operators in a 300mm fab, too few to matter. Wafers are all moved in FOUPs by overhead transport systems so idle no operator is a thing of the past, Decisions on what to process are all handled by automation too.
I believe unscheduled down time is the biggest issue. It...
I would also say the state of the art fabs get to mature manufacturing performance in the first year or so and after that improvements are incremental, not "huge".
I disagree, a well designed fab will balance the tools across the fab to the greatest extent possible because the "constraint" will move, designing a deliberate constraint under utilizes everything else. How well that can be done is highly dependent on the fab size, the bigger the fab the better...
