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I don't know why they couldn't have said something like "it's even better than Meteor Lake yield at launch" rather than the whole qualifying statement.
Country’s government says deal with TSMC needs state assessment and it may protect its most advanced tech
Helen Davidson in Taipei Tue 4 Mar 2025 12.20 GMT
Taiwan’s government has suggested a $100bn semiconductor deal between Donald Trump and the Taiwanese chip maker TSMC is not guaranteed...
The 18A process was already delayed to 2026 for potential contract manufacturing customers. Now, according to supplier documents reviewed by Reuters and two sources familiar with the matter, Intel has pushed back its timeline another six months.
The delay is due to the need to qualify crucial...
While Intel Foundry is not split off from Intel Product, there's always the concern for AMD, Nvidia, or Apple that their designs are not completely safe when handed over to Intel Foundry, or that their business will not get sufficient priority compared to Intel Product. After all, Intel Product...
It seems this formula has been around for years, but not necessarily followed (from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm):
Going directly by the picture, it works out to 1.56 transistors/CPP/Cell height.
It hasn't been followed by everyone obviously. One example is Wikichip...
If the "earlier" machines are the previous EUV NA, he might be talking about ~ 20 nm pitch.
imec had just released some results for 20 nm pitch: https://www.imec-int.com/en/press/imec-demonstrates-electrical-yield-20nm-pitch-metal-lines-obtained-high-na-euv-single, still rough as expected...
Looking at some prior but recent generations' SRAM design examples, of course they were frontside but they had Vss and Vdd lines on different metal layers. This is unlike the standard logic arrangement of both Vss and Vdd on same layer. I wonder if backside routing could not support so many...
I'm not saying it couldn't have been expected, just that it was odd to put this counter-spin to PowerVia at this time. I guess it means PowerVia will only be implemented in non-SRAM sections of the chip.
Samsung to increase next-generation DRAM 'chip size'... HBM Yield Improvement Priority
Weigh in on yield stabilization instead of productivity... Earnings expected by the end of the second quarter
Semiconductor Display Input:2025/02/10 17:05 Modified: 2025/02/11 10:09
Jang Kyung-yoon
It is...
