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Search results

  1. F

    Nvidia announces Taiwan HQ in Taipei

    TAIPEI (Taiwan News) — Nvidia CEO Jensen Huang (黃仁勳) announced Monday at Comptex that the company’s new overseas headquarters will be built in Taipei’s Beitou-Shilin area, ending months of speculation and signaling a major expansion in Taiwan. Dubbed “Nvidia Constellation,” the new office is...
  2. F

    High NA EUV Equipment is Bound to be a Burden for Chipmakers

    The author is asking for a vendor's bias by not also talking to customers. They're also not attending the events like SPIE.
  3. F

    Stitched multipatterning for routing metal, even within era of EUV, for 2nm and beyond

    As the semiconductor process further scales down to 2nm and beyond, the multi-patterning technology has emerged as the clear choice of the routing metal layers even within the era of extreme ultraviolet (EUV) lithography. The stitching technique within multi-patterning can divide a node into...
  4. F

    High NA EUV Equipment is Bound to be a Burden for Chipmakers

    I know the guy, he's an intense history buff (Asianometry channel covers many interesting historical episodes, not just technological). But in the complete picture, it isn't enough to only consider the response of the resist to the EUV radiation. You also have to consider the EUV-induced...
  5. F

    TSMC Discloses N2 Defect Density Lower Than N3 At The Same Stage Of Development

    Yes, I remember seeing the same report, a D0 of 1.5 would give 30% yield for a 9 mm x 9 mm chiplet. But this is for an SRAM macro. It might be different for other chips: https://www.digitimes.com/news/a20250325PD228/tsmc-2nm-fab-yield-rate-2025.html
  6. F

    High NA EUV Equipment is Bound to be a Burden for Chipmakers

    I've always felt EUV R&D should be more exhaustive before implementing in high volume. The amount of R&D wafers needed could be or should be millions. The list of questions practically has no end. Here we have undesired exposure to EUV-induced plasma electrons from different exposed fields...
  7. F

    High NA EUV Equipment is Bound to be a Burden for Chipmakers

    High-NA adds 3 new problems Low-NA doesn't have: (1) reduced depth of focus (so need much thinner resist films); (2) the 104 mm x 132 mm mask area maps to a 26 mm x 16.5 mm wafer exposure field instead of the conventional 26 mm x 33 mm; (3) central obscuration will limit some combinations of...
  8. F

    Samsung targets 2nm orders from Nvidia, Qualcomm to boost foundry position

    With no backside power delivery yet, and yield reports still not encouraging, it's a surprise they can still draw customers.
  9. F

    Samsung targets 2nm orders from Nvidia, Qualcomm to boost foundry position

    As 3nm GAA yields stabilize, Samsung Electronics fcuses on 2nm process to narrow TSMC's lead By Chun Byung-soo, Kim Seo-young Published 2025.05.13. 16:09 Samsung Electronics’ foundry division is reportedly nearing the final stage of evaluating its 2-nanometer (nm) process with Nvidia and...
  10. F

    Could Intel Be Delaying the Foundry Competition to 14A

    Actually the proposed 18A use was reported a while back in Feb (https://www.reuters.com/technology/intel-says-first-two-new-asml-machines-are-production-with-positive-results-2025-02-24/), but it seems now the update is they would only consider it for a few layers of 14A. Maybe they don't have...
  11. F

    Could Intel Be Delaying the Foundry Competition to 14A

    Less depth of focus for same design rule, why do that?
  12. F

    Darth Vader in Semiconductor Industry?How the Turncoat and the Loyalist of TSMC Shaped the Global Chip War

    TSMC had done it better than Intel. Not sure if it's the same way SMC does it.
  13. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    FWIW, NA is not figuring into EUV practical resolution. It's resist-limited at this point. https://www.spiedigitallibrary.org/conference-proceedings-of-spie/13424/1342403/NA033-EUV-extension-for-HVM-testing-single-patterning-limits/10.1117/12.3052244.full
  14. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    Yes, direct print meant single exposure instead of multipatterning, in their context.
  15. F

    TSMC vs Intel track pitch scaling trend

    Tracks are conventionally M2, but Intel uses M0 apparently, at least for Intel 3/4.
  16. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    So the oft-mentioned 40 steps is for the no High-NA contingency at 14A, then?
  17. F

    EUV productivity not the same across the field

    TSMC and ASML both reported that source power upgrades were not trivial, as pellicle damage tolerances need to be considered.
  18. F

    EUV productivity not the same across the field

    Not all EUV machines in use are equally productive. Old/new mix. Abstract ASML has been making steady advances in Extreme Ultraviolet (EUV) light source capability for more than 15 years. Since introduction of the 250W EUV light source in 2018, which ushered in the era of EUV High Volume...
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