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Will Memory Chiplets Dominate

nghanayem

Active member
3D nand is not the same as 3D stacking of logic dies. Logic people are stacking dies ontop of some base die (similar to hbm stacked on a cpu/gpu or meteor lake tiles ontop of a forvoros die). 3D nand is basically a similar deal to what happened in cities. Due to physical limitations nand flash cells could not be made any smaller. To get around this the transistors were turned on their sides and stacked; allowing for multiple "floors" of transistors in a similar manner to a skyscraper.
1664726624514.png

MCM designs (in a similar manner to what is happening with logic) will never reach the same ubiquity that it likely will with logic. The only real applications for this are stacked dram solutions like HBM and whatever the TSMC name for V-cache is. Stacking nand flash doesn't really make any sense given how slow it is (PCIE is fine for this application). Of course they will still use traditional multi die packaging techniques (just look at any stick of dram or nvme ssd), but I assume you weren't talking about or interested in these techniques.
 
Last edited:

Arthur Hanson

Well-known member
3D nand is not the same as 3D stacking of logic dies. Logic people are stacking dies ontop of some base die (similar to hbm stacked on a cpu/gpu or meteor lake tiles ontop of a forvoros die). 3D nand is basically a similar deal to what happened in cities. Due to physical limitations nand flash cells could not be made any smaller. To get around this the transistors were turned on their sides and stacked; allowing for multiple "floors" of transistors in a similar manner to a skyscraper.
View attachment 928
MCM designs (in a similar manner to what is happening with logic) will never reach the same ubiquity that it likely will with logic. The only real applications for this are stacked dram solutions like HBM and whatever the TSMC name for V-cache is. Stacking nand flash doesn't really make any sense given how slow it is (PCIE is fine for this application). Of course they will still use traditional multi die packaging techniques (just look at any stick of dram or nvme ssd), but I assume you weren't talking about or interested in these techniques.
Thanks for the excellent post.
 
Chiplet approach these days mostly means emulating monolithic power-perf while keeping separate manufacturing facilities. Most memory applications don't really need that because memory doesn't need to be integrated 'together'. CPU or GPU(any controllers) can access memory wherever they are and that doesn't make any problem.
The only exception these days is HBM, where high bandwidth per die is required due to power-perf and space(and lack of PCB spaces).
 
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