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Why wasn’t the “Intel Smithfield” method of two CPU dies used for 12-16 core Ryzen?


Well-known member
If I understand correctly, Intel used a single wafer for both single core Pentium 4 and dual core Pentium D dies. They achieved this by slicing the wafer up according to needs — two adjacent dies for Pentium D, and any single die for Pentium 4.

I’m curious if this was ever considered or would make any sense for Ryzen 12 and 16 core purposes. I’m thinking:

+ Two dies next to each other should have significantly lower energy per joule for data transferred between the dies (than a substrate), addressing a drawback to current 12 and 16 core Ryzens since Zen 2.

+ Cross-die latency improvements vs. routing through a substrate

+/- If you have a less than perfect yield with either or both dies, you can still ‘downsize’ to a 12 core or lower clocked 12 core. You could potentially even have an 8 core with 2 working 4+4 dies.

+/- complexity when adding in a ‘3rd’ die for SoC — + in that you need to choose which (or both) of the dies can communicate with the SoC, - in that the two dies are already ‘pre wired to each other’, meaning less demand on the substrate.

- Testing performance of a larger ‘double die’ is a more complex process than two single (smaller) dies

Thoughts? If my thinking is stupid please let me know :)


Per wikipedia:
The 90 nm"Smithfield" contains a single die, with two adjoined but functionally separate CPU cores cut from the same wafer.