When Shrink Ends, Graphene inteconnected Processors, TSM rules

[Arthur Hanson]

Graphen based wireless interconnected processors look the next frontier after shrink, which is rapidly reaching its limits. This looks like an entirely new frontier for semis that is just in its very early stages. This and interconnected chiplets look like the next frontier and expect TSM to be the leader in this area to maintain themselves as the undisputed leader of the semi industry. It's no secret that TSM is already a leader in this area. Any thoughts, comments, or additions solicited on this subject.

https://arxiv.org/pdf/2011.04107.pdf

 

[BlueNode]

What struck you about this paper in particular? It's a ten year old paper mostly by European graduate students. It doesn't seem like anything real, just an academic publication. The idea of wireless interconnects on a chip is strange, and their first table shows that "optics" (silicon photonics?) is much faster and more efficient. I didn't read the rest of the paper, so I don't know what their argument for wireless interconnects comes down to. You'd be giving up so much to switch from physical interconnects to wireless, and inviting all kinds of noise and EMI issues, among other things.

So far nothing has happened with graphene, or with nanotubes. I'm not sure why, but it just hasn't borne fruit yet. On the nanotube side, Nantero keeps missing their dates and failing to deliver on any of their promises, which is disappointing. We might need bigger thinking to bypass some of the issues people are running into. For example, Nantero tries to put nanotubes on a silicon wafer... The way the industry is locked into thinking of chips as things you make from silicon wafers is probably holding us back.

 

[Arthur Hanson]

What struck you about this paper in particular? It's a ten year old paper mostly by European graduate students. It doesn't seem like anything real, just an academic publication. The idea of wireless interconnects on a chip is strange, and their first table shows that "optics" (silicon photonics?) is much faster and more efficient. I didn't read the rest of the paper, so I don't know what their argument for wireless interconnects comes down to. You'd be giving up so much to switch from physical interconnects to wireless, and inviting all kinds of noise and EMI issues, among other things.

So far nothing has happened with graphene, or with nanotubes. I'm not sure why, but it just hasn't borne fruit yet. On the nanotube side, Nantero keeps missing their dates and failing to deliver on any of their promises, which is disappointing. We might need bigger thinking to bypass some of the issues people are running into. For example, Nantero tries to put nanotubes on a silicon wafer... The way the industry is locked into thinking of chips as things you make from silicon wafers is probably holding us back.

Thanks for the information, graphene I feel is a new frontier that will find more and more uses in everything with many successes and failures, just like every other new technology. One advantage is carbon is cheap and everywhere.

 

[IanD]

Thanks for the information, graphene I feel is a new frontier that will find more and more uses in everything with many successes and failures, just like every other new technology. One advantage is carbon is cheap and everywhere.

But silicon is cheap and everywhere too. However TSMC-5nm-class silicon isn't...

 

[dwisehart]

I have been impressed that as the size shrinks and the number of transistors per mm goes up, the cost goes up a little faster than the shrink goes down, but not a lot. So the cost for a million transistors is staying about the same. At least from 40nm to 12nm to 7nm. I can believe there are higher prices per transistor at 5nm and at 3nm.

 

[IanD]

I have been impressed that as the size shrinks and the number of transistors per mm goes up, the cost goes up a little faster than the shrink goes down, but not a lot. So the cost for a million transistors is staying about the same. At least from 40nm to 12nm to 7nm. I can believe there are higher prices per transistor at 5nm and at 3nm.

Cost per transistor (more accurately, per gate) is still dropping 7nm==>5nm==>3nm, gate density is going up faster than wafer prices. Cost drop per node is smaller than it used to be because of this but still significant, if it wasn't nobody would want to use the latest process...

 

[IanD]

NRE (mask) and design costs are another matter entirely, they're rising exponentially -- this is what I meant when I said "TSMC 5nm isn't cheap", like a Rolls-Royce if you have to ask the cost you can't afford it... ;-)