You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
When in the manufacturing process do wafer lots get divided up?
If there is a lot of 25 wafers from the fab, will it usually stay together all the way through the back-end? or would a single wafer get taken from die bank and put through back-end processing?
(alternative way of asking: is the unit of back-end processing equal to 1 wafer lot or 1 wafer?)
When in the manufacturing process do wafer lots get divided up?
If there is a lot of 25 wafers from the fab, will it usually stay together all the way through the back-end? or would a single wafer get taken from die bank and put through back-end processing?
(alternative way of asking: is the unit of back-end processing equal to 1 wafer lot or 1 wafer?)
For production lots, it usually keeps all 25 wafers together, unless some wafers are scrapped due to process issues. For military grade wafers, there will be definition of lot scrapped when total wafer number are lower than 25 (ex. 20 wafers survived in some event, then all other good wafers should be scrapped also). For some design, they might have different versions running different mask set combinations, some wafers run at specific version will be split and run to the end. For pilot lot, you might split wafers for design verification or process window qualification, then small lots will be created.
For military grade wafers, there will be definition of lot scrapped when total wafer number are lower than 25 (ex. 20 wafers survived in some event, then all other good wafers should be scrapped also).
Logical reason would be a combination of tests being less than 100%, and all wafers shared same processing experience. So if a significant fraction failed then there remains risk that whatever systematic failure was detected in those was likely affecting the rest of the batch, so while they might have escaped the test they may carry increased risk if shipped to the field.
In memory we have ECC which can catch errors in operation. In logic circuits there is generally no self-test, so the creation of highly reliable parts over extended lifetimes can only be approached by paranoid test procedures which attempt to ensure the logic is way above thresholds, giving margins that will hold safe for years, since most post-manufacture errors will be undetected.
