What is the most advanced (dense?) logic process that flies in Space?

[Xebec]

Just curious - what is considered the highest end logic process that flies in space? Do we always use ‘rad hardened designs’, or do we sometimes use OTS / commercial stuff and just a lot of shielding around it?

 

[cliff]

That was the original "Why FDSOI" question. Tanj says "Forget the lead shield. Go for redundancy"

 

[Tanj]

That was the original "Why FDSOI" question. Tanj says "Forget the lead shield. Go for redundancy"

Error detection and retry/ECC are good too.

Your process has to tolerate charge bursts without lockup or fusing, no permanent damage from the common events. Bonus points for shrugging off charge bursts without error, like DRAM does.

 

[IanD]

Just curious - what is considered the highest end logic process that flies in space? Do we always use ‘rad hardened designs’, or do we sometimes use OTS / commercial stuff and just a lot of shielding around it?

There's certainly standard (not rad-hardened) commercial OTS 7nm CMOS up there. Don't know how it's shielded though... ;-)

 

[hist78]

Just curious - what is considered the highest end logic process that flies in space? Do we always use ‘rad hardened designs’, or do we sometimes use OTS / commercial stuff and just a lot of shielding around it?

From this old article, the ICs for the Perseverance Mars rover are radiation-hardened.

Power tech in the Perseverance Mars rover

Power design is critical in the latest Mars rover which is expected to last at least one Mars year, about 687 days on Earth.

www.eenewseurope.com

 

[Tanj]

There are papers on this if you search. Here is an example: https://radhome.gsfc.nasa.gov/radhome/papers/MRQW2011_Pellish.pdf

I would suggest you talk to customers interested in that market and ask them what/who they use for certification. That may lead you to people who are fluent in the technology options and tradeoffs.

 

[M. Y. Zuo]

Probably SpaceX stuff since they use COTS as much as possible and go for redundancy.

 

[Tanj]

Probably SpaceX stuff since they use COTS as much as possible and go for redundancy.

Also they seem to de-orbit sats within a few years due to aggressive upgrades as they are learning from experience and willing to discard the trailing edge. Perhaps they will need more durability when they are confident enough in their design to put up the full 30k swarm.

 

[IanD]

Probably SpaceX stuff since they use COTS as much as possible and go for redundancy.

That's why I mentioned 7nm commercial silicon... ;-)

 

[IanD]

Also they seem to de-orbit sats within a few years due to aggressive upgrades as they are learning from experience and willing to discard the trailing edge. Perhaps they will need more durability when they are confident enough in their design to put up the full 30k swarm.

IIRC the issue isn't really durability, it's SEU. But no way are SpaceX going to spend a fortune -- and greatly increase TTM -- having customised chips developed for all the electronics in their satellites, they'll take existing stuff they can get hold of and radiation test it. DAMHIK... ;-)