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What is the current status and outlook of FinFETs/GaaFETs on FD-SOI?

TernexE

New member
It is my understanding that chip producers that want to further scale their chips essentially have two options going forward:

1. Adopt 3D technology using FinFETs/GaaFETs
2. Adopt SOI technology using planar transistors

Obviously, the choice between these options depends on many factors (costs, ecosystem, technical aspects etc.), but both have in common that at some point further innovation will be needed to continue scaling.

Now regarding option 2: Is there a way to continue scaling SOI technology by moving to FinFETs/GaaFETs on SOI at some point in the future? What is the current status here and what's the outlook in your opinion?
 
Now regarding option 2: Is there a way to continue scaling SOI technology by moving to FinFETs/GaaFETs on SOI at some point in the future? What is the current status here and what's the outlook in your opinion?

I don't think so.

By the time you get to nanosheet GAA, you have gates completely surrounding the active channels.

I don't see much advantage to having GAAFET fabricated on SOI wafers, or fully-depleted SOI wafers.

(FinFET on SOI was looked at a few years back. But the industry is going nanosheet/ GAA next).


After the first round of GaaFET, the roadmap is the CFET structure I think.
 
FinFET on SOI was looked at a few years back. But the industry is going nanosheet/ GAA next
Ok, thanks! Would it be fair to say that FinFETs/GAAFETs (and CFETs) on bulk wafers will be the main choice for cutting-edge nodes (5nm and below), whereas planar FETs on SOI wafers will be the dominant technology for trailing edge nodes (10nm and above)?
 
Ok, thanks! Would it be fair to say that FinFETs/GAAFETs (and CFETs) on bulk wafers will be the main choice for cutting-edge nodes (5nm and below), whereas planar FETs on SOI wafers will be the dominant technology for trailing edge nodes (10nm and above)?

2D TMD and CNT have been mentioned as a follow-on to GAA and CFET. We should know more after the upcoming VLSI Conference and TSMC Technical Symposium next week so stay tuned.
 
Yes, these will likely only be used at cutting edge nodes below 3nm, right? What about the nodes 10nm and above? Will they converge towards SOI?

TSMC did not embrace SOI so I would say no. Samsung has SOI but I have not heard if they stopped at 28nm or continued. Samsung is also focused on the leading edge. GF of course has FD-SOI.
 
TSMC did not embrace SOI so I would say no. Samsung has SOI but I have not heard if they stopped at 28nm or continued. Samsung is also focused on the leading edge. GF of course has FD-SOI.
If nodes at 10/16/24nm and higher won't necessarily move to SOI, what will they do instead to continue scaling/improving? For some applications (e.g. analog low-power RF chips) moving to cutting-edge nodes doesn't really make sense, right? Or do you disagree here?
 
If nodes at 10/16/24nm and higher won't necessarily move to SOI, what will they do instead to continue scaling/improving? For some applications (e.g. analog low-power RF chips) moving to cutting-edge nodes doesn't really make sense, right? Or do you disagree here?
In terms of technologies in play for RF (cellular / WiFi use cases), Samsung 14LPC and TSMC N16/12FFC (both FinFET on bulk) are already in production and shipping in market as transceivers (Qualcomm, Samsung modem business). These foundries have RF optimized versions of their N6 and S8 nodes (public disclosures) for the next generation solutions, so there is already a scaling path available for those markets. For single-chip radio solutions (TWS, IoT markets, etc) the issue is less the RF support and more the eNVM support, since many of those applications are MCUs that have some programmable firmware required, and for the current 65/45 gen parts they have eFlash for this function (cheaper than doing an MCM with a NOR Flash die).

28nm the eFlash did not scale as well (initially, there may still be a path here based on some publications) and so other eNVM technologies like STT-MRAM or RRAM were pursued instead. Magnetic RAM + RF obviously can pose a challenge there, but that seems to be what most of the Foundries have offered for the ~28nm generation of eNVM. Nodes below do not currently offer (that I'm aware of), but the STT or SOT or RRAM structure is within the BEOL anyhow so should be portable to newer technologies, though it may not scale in the min CDs, so density improvement based on literature is focused on bit stacking or multi-bit resolution (like NAND Flash having dual/tri/quad state per bit). The actual storage element (Magnetic Tunnel Junction: https://www.spintronics-info.com/introduction-stt-mram) requires a number of process layers at various Angstrom-level deposition, so the cost adder to the wafer is non trivial.

For FD-SOI, this is currently 'parked' along with single-patterned BEOL metals, so 28/22nm nodes. GF had offered their 18FDSOI which would have (IIRC) moved some lower BEOL to double-patterned metal pitches (still a planar FET), but not clear that ever went into production. The challenge (my opinion) is that they don't offer substantial density or performance benefits against the N16/12 or S14 nodes to be competitive there, and they have a cost floor from the SOI wafer (more expensive than Bulk) that means they can't really undercut just on price. But there may be plenty of markets for which 28/22 FDSOI is the ideal PPASC and migrating the design environment to a FinFET / multi-patterning regime is prohibitive, even if the PPA might be better on paper.
 
Thanks very much for this detailed answer!

But there may be plenty of markets for which 28/22 FDSOI is the ideal PPASC and migrating the design environment to a FinFET / multi-patterning regime is prohibitive, even if the PPA might be better on paper.
I suppose the main reason for not migrating the design environment to FinFET/multi-patterning is higher cost, correct? Ignoring the cost aspect, are there also technical reasons?

But there may be plenty of markets for which 28/22 FDSOI is the ideal PPASC
Do you have a (rough) estimation for the fraction of the semiconductor market that SOI technology could capture long-term?
 
I suppose the main reason for not migrating the design environment to FinFET/multi-patterning is higher cost, correct? Ignoring the cost aspect, are there also technical reasons?
Do you have a (rough) estimation for the fraction of the semiconductor market that SOI technology could capture long-term?
Negative on market size. Design environment, it is not cost (EDA etc) it is 'new thinking'. Colored metals from multi patterning introduce different RC issues; fins are quantized so makes adjusting gain or drive more cumbersome, etc. So there is a learning curve to designing analog / RF once you move away from planar / single patterned metals, and for some companies they may not want to invest in that step-function. Obviously for the bigger players they have been doing this for nearly a decade, so it is certainly possible, just a potential barrier for smaller companies / IP providers who may not have the expertise in house.
 
Planar FDSOI can only scale a few nodes, even FDSOI pioneer CEA/LETI had their scaling roadmap being FDSOI and then GAA takes over.

FinFETs are higher performance for leading edge applications and have scaled a lot faster than FDSOI.

You can make a FinFET on SOI, in fact IBM 14nm was FinFET on SOI and GF may be still running a few wafers that way for IBM. There have also been papers about CFETs on SOI.

SOI is used a lot for RF, pretty much every cell phone made has SOI in the front end. FDSOI has some interesting advantages in certain applications but it is, and probably always be a small part of the overall semiconductor market.

Cost has always been a big draw back.
 
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