What is really going on with Intel’s 18a process?

[XYang2023]

Intel is in deep trouble, the 18a process is broken, and it is all down hill from here, right? SemiAccurate dug deeply into the 18a rumors for the last 3+ weeks and hunted them all down.

As you may recall, SemiAccurate was the first, and for years only site that was screaming about Intel’s 10nm problems, with data. Only after it became undeniable did other climb on board. SemiAccurate also called Intel’s potential for outright failure in 2019, again long before anyone else did. We have a long track record of calling Intel’s problems and their successes because we do the groundwork and research rather than parroting back random idiots on the net.

What is really going on with Intel’s 18a process?

Intel is in deep trouble, the 18a process is broken, and it is all down hill from here, right?

www.semiaccurate.com

 

[kevin01]

Anyone has a subscription to post the key takeaways? I used to have a sub to SA, but not anymore.

 

[XYang2023]

"Believe it or not even with all this smoke there is actually a fire but it probably isn’t what you think."

What could be the "fire"? The sentiment of the sentence seems to be neutral/positive.

 

[hskuo]

Intel's statement that D0 of 18A is less than 0.4 actually demonstrated that some milestone has been achieved, no matter it was from test vehicle of SRAM, CPU core or others.

 

[Daniel Nenni]

"Believe it or not even with all this smoke there is actually a fire but it probably isn’t what you think."
What could be the "fire"? The sentiment of the sentence seems to be neutral/positive.

There are two problems with 18A, the extremely high expectations Intel set and the PDK.

I am close to the ecosystem and the ecosystem does not lie. The PPA of 18A is in serious question. It is fun to quote numbers based on SRAM and other test structures but when you try and design a complex SoC or a big fat AI chip the power, performance and area numbers come up differently. Power is an especially tricky one. TSMC on the other hand is an expert at setting customers expectations and low power is their specialty. How many years has TSMC been manufacturing mobile SoCs?

In regards to yield, if you compare TSMC yield to Intel yield, Intel has ALWAYS had a yield problem. The same with Samsung, even more so of late.

Bottom line: The ONLY solution to Intel's manufacturing problems is to stop comparing them to TSMC. It really is a different animal: Pure-Play foundry versus an IDM foundry. Comparing TSMC to Intel is like comparing SemiWiki to Semiaccurate.

 

[kevin01]

There are two problems with 18A, the extremely high expectations Intel set and the PDK.

I am close to the ecosystem and the ecosystem does not lie. The PPA of 18A is in serious question. It is fun to quote numbers based on SRAM and other test structures but when you try and design a complex SoC or a big fat AI chip the power, performance and area numbers come up differently. Power is an especially tricky one. TSMC on the other hand is an expert at setting customers expectations and low power is their specialty. How many years has TSMC been manufacturing mobile SoCs?

In regards to yield, if you compare TSMC yield to Intel yield, Intel has ALWAYS had a yield problem. The same with Samsung, even more so of late.

Bottom line: The ONLY solution to Intel's manufacturing problems is to stop comparing them to TSMC. It really is a different animal: Pure-Play foundry versus an IDM foundry. Comparing TSMC to Intel is like comparing SemiWiki to Semiaccurate.

Well said. Intel's own presentation matches what you described.

1. Intel admitted that it would not compare favorably in terms of power against TSMC processes until 14A (which has a tremendous amount of uncertainty). This is indeed a big disadvantage, since much of industry (even HPC customers such as NVDA and AMD) emphasizes lowering power usage.

2. It only announced two internal products based on 18A so far, one is Panther Lake, another is Clearwater Forest. PTL's largest compute tile is only 1.2 cm^2, and CWF's compute tiles are even smaller. This is not an accident, because big fat chips requires much higher yields. It remains to be seen when IFS can improve their yields from D0 of 0.4 to 0.2, or even 0.1.

I can see several positives:

1. Intel 3 seems to be doing well, producing large chips such as Granite Rapids on time. And the yield improvement from Intel 4 seems to be significant, as Intel 4 was only used to produce very small MTL compute tiles (~0.4 cm^2 die size).

2. From a technical point of view, the current management and IFS team seems to have learned their lessons in late 2010s, largely hitting their goals.

3. IFS does not need large amount of external customers to sustain itself financially for a while. In the next 2-3 years, they just need a few external customers to help prove that its PDK, its tools, and its service level are good enough; but these customers does not need to be whales.

4. TSMC seems to be also slowing (N5 -> N3E takes about 3 years). The improvements are harder and harder to come by in general.

 

[Fred Chen]

They tried pattern shaping and the results before and after were less than satisfactory: https://www.spiedigitallibrary.org/...-at-Intel-18A-process/10.1117/12.3010982.full

 

[tooLongInEDA]

Well said. Intel's own presentation matches what you described.

1. Intel admitted that it would not compare favorably in terms of power against TSMC processes until 14A (which has a tremendous amount of uncertainty). This is indeed a big disadvantage, since much of industry (even HPC customers such as NVDA and AMD) emphasizes lowering power usage.

2. It only announced two internal products based on 18A so far, one is Panther Lake, another is Clearwater Forest. PTL's largest compute tile is only 1.2 cm^2, and CWF's compute tiles are even smaller. This is not an accident, because big fat chips requires much higher yields. It remains to be seen when IFS can improve their yields from D0 of 0.4 to 0.2, or even 0.1.

I can see several positives:

1. Intel 3 seems to be doing well, producing large chips such as Granite Rapids on time. And the yield improvement from Intel 4 seems to be significant, as Intel 4 was only used to produce very small MTL compute tiles (~0.4 cm^2 die size).

2. From a technical point of view, the current management and IFS team seems to have learned their lessons in late 2010s, largely hitting their goals.

3. IFS does not need large amount of external customers to sustain itself financially for a while. In the next 2-3 years, they just need a few external customers to help prove that its PDK, its tools, and its service level are good enough; but these customers does not need to be whales.

4. TSMC seems to be also slowing (N5 -> N3E takes about 3 years). The improvements are harder and harder to come by in general.

View attachment 2257

Surely (your point #2) this is not great news for Intel in terms of filling 18A capacity if they can only run small[er] tiles for power/yield/cost reasons ? May also lead to more/continued use of TSMC ?

 

[kevin01]

Surely (your point #2) this is not great news for Intel in terms of filling 18A capacity if they can only run small[er] tiles for power/yield/cost reasons ? May also lead to more/continued use of TSMC ?

They are continuing to improve the yield. Ultimately, the success of 18A will be decided by how high the yields are, and how rich its ecosystem (e.g. PDK and tools) are.

I will watch their future announcements as signals regarding 18A health:

1 panther lake production date, the earlier the better.

2 new intel products (such as diamond rapids) announcement using 18A. This would indicate their yield improves to a level such that large Xeon cpus can be manufactured using 18A.

 

[siliconbruh999]

Intel will regain it's process leadership in the same exact way it lost it that is TSMC makes a wrong bet no other way

 

[dkr1986]

They are continuing to improve the yield. Ultimately, the success of 18A will be decided by how high the yields are, and how rich its ecosystem (e.g. PDK and tools) are.

I will watch their future announcements as signals regarding 18A health:

1 panther lake production date, the earlier the better.

2 new intel products (such as diamond rapids) announcement using 18A. This would indicate their yield improves to a level such that large Xeon cpus can be manufactured using 18A.

Regarding Xeon CPUs on 18A, Intel already announced E core based Clearwater Forrest (aka XEON 7E?) that will be on Intel 18A to be released in 2H'2025. But I guess you are looking for new announcement of P core based Xeon on 18A.

 

[siliconbruh999]

Regarding Xeon CPUs on 18A, Intel already announced E core based Clearwater Forrest (aka XEON 7E?) that will be on Intel 18A to be released in 2H'2025. But I guess you are looking for new announcement of P core based Xeon on 18A.

The thing is they are almost <1cm2 die size so easy to yield it's meteor lake strategy all over they will be using small die to get yield up quicker Intel 3 is very good now cause it can produce 580mm2 die which is not a joke Intel 7 also must have very good yield for therir EMR die size 18A no one is sure only time can tell

 

[delong.height]

There are two problems with 18A, the extremely high expectations Intel set and the PDK.

I am close to the ecosystem and the ecosystem does not lie. The PPA of 18A is in serious question. It is fun to quote numbers based on SRAM and other test structures but when you try and design a complex SoC or a big fat AI chip the power, performance and area numbers come up differently. Power is an especially tricky one. TSMC on the other hand is an expert at setting customers expectations and low power is their specialty. How many years has TSMC been manufacturing mobile SoCs?

In regards to yield, if you compare TSMC yield to Intel yield, Intel has ALWAYS had a yield problem. The same with Samsung, even more so of late.

Bottom line: The ONLY solution to Intel's manufacturing problems is to stop comparing them to TSMC. It really is a different animal: Pure-Play foundry versus an IDM foundry. Comparing TSMC to Intel is like comparing SemiWiki to Semiaccurate.

Well, They have to compare to TSMC, comparing to TSMC isn't Intel's failure. The fact is that there isn't another trustable competitor you can compare to. Samsung, sure if you don't want to be the best.

 

[kevin01]

Regarding Xeon CPUs on 18A, Intel already announced E core based Clearwater Forrest (aka XEON 7E?) that will be on Intel 18A to be released in 2H'2025. But I guess you are looking for new announcement of P core based Xeon on 18A.

+1 to what siliconbruh999 said.

A Clearwater Forest chip consists of 14 small chiplets, so it should yield quite well (probably even better than PTL) on the wafer level. However, the challenge is to do 3D chip stacking of so many chiplets.

A few weeks ago, IFS head said PTL yielded well, but did not use the same language for CWF. My speculation is that their 3d stacking technology was the bottleneck.

 

[name99]

"Believe it or not even with all this smoke there is actually a fire but it probably isn’t what you think."

What could be the "fire"? The sentiment of the sentence seems to be neutral/positive.

18A is conceptually
- the usual smaller everything AND
- RibbonFET AND
- PowerVia

I could believe that two of these three are adequate, and Intel is trying to figure out which looks worse – shipping an "18A" with two of the three, or delaying until the third actually works...

If I had to guess, purely based on historical pattern matching, my money would be on PowerVia being the troublemaker.

 

[name99]

Well said. Intel's own presentation matches what you described.

1. Intel admitted that it would not compare favorably in terms of power against TSMC processes until 14A (which has a tremendous amount of uncertainty). This is indeed a big disadvantage, since much of industry (even HPC customers such as NVDA and AMD) emphasizes lowering power usage.

2. It only announced two internal products based on 18A so far, one is Panther Lake, another is Clearwater Forest. PTL's largest compute tile is only 1.2 cm^2, and CWF's compute tiles are even smaller. This is not an accident, because big fat chips requires much higher yields. It remains to be seen when IFS can improve their yields from D0 of 0.4 to 0.2, or even 0.1.

I can see several positives:

1. Intel 3 seems to be doing well, producing large chips such as Granite Rapids on time. And the yield improvement from Intel 4 seems to be significant, as Intel 4 was only used to produce very small MTL compute tiles (~0.4 cm^2 die size).

2. From a technical point of view, the current management and IFS team seems to have learned their lessons in late 2010s, largely hitting their goals.

3. IFS does not need large amount of external customers to sustain itself financially for a while. In the next 2-3 years, they just need a few external customers to help prove that its PDK, its tools, and its service level are good enough; but these customers does not need to be whales.

4. TSMC seems to be also slowing (N5 -> N3E takes about 3 years). The improvements are harder and harder to come by in general.

It's not just that "it's getting harder for everyone", it's also "who has better competence to handle this environment".
TSMC has a long history of
(a) cautiously rolling out one improvement at a time. With a plan-B (eg N3B vs N3E) lined up if required.
(b) not saying anything publicly until the details are worked out and everything is ready.
This means they mostly deliver what they promise, both to customers and to Wall Street.

Meanwhile Intel, uh, not so not much on either of these. Intel is the sloppy drunk at a bar telling everyone who will listen "I'm a gonna build my own GAA. And my own BSPD. And I'm gonna do it in two years, in the same product because I'm just that good. And five years from now I'm gonna be delivering CFETs. And eight years from now I'm gonna shipping graphene chips. Just you wait. Burp. I'm a sleepy now."

Intel's particular style of clueless self-aggrandizement is a singularly terrible match for an environment of slow, patient (and unpredictable!) improvement. Again, for both its customers and Wall Street.

 

[name99]

They are continuing to improve the yield. Ultimately, the success of 18A will be decided by how high the yields are, and how rich its ecosystem (e.g. PDK and tools) are.

I will watch their future announcements as signals regarding 18A health:

1 panther lake production date, the earlier the better.

2 new intel products (such as diamond rapids) announcement using 18A. This would indicate their yield improves to a level such that large Xeon cpus can be manufactured using 18A.

No, it's also how well the process meets the requirements of customers.

If Intel optimizes for GHz (as they always have in the past) but what foundry customers primarily want is density and low power, that's not a great match.
And if the only way Intel can get anyone to pay them for a less desirable process is by charging below cost, well, that's an "interesting" business model.

 

[Daniel Nenni]

Well, They have to compare to TSMC, comparing to TSMC isn't Intel's failure. The fact is that there isn't another trustable competitor you can compare to. Samsung, sure if you don't want to be the best.

Vaulting an impossibly high bar is fine in theory but in practice it can really hurt, especially if everyone is betting that you will clear it.

 

[kevin01]

18A is conceptually
- the usual smaller everything AND
- RibbonFET AND
- PowerVia

I could believe that two of these three are adequate, and Intel is trying to figure out which looks worse – shipping an "18A" with two of the three, or delaying until the third actually works...

If I had to guess, purely based on historical pattern matching, my money would be on PowerVia being the troublemaker.

You are guessing powervia, because tsmc or samsung were not able to do it yet?

 

[kevin01]

It's not just that "it's getting harder for everyone", it's also "who has better competence to handle this environment".
TSMC has a long history of
(a) cautiously rolling out one improvement at a time. With a plan-B (eg N3B vs N3E) lined up if required.
(b) not saying anything publicly until the details are worked out and everything is ready.
This means they mostly deliver what they promise, both to customers and to Wall Street.

Meanwhile Intel, uh, not so not much on either of these. Intel is the sloppy drunk at a bar telling everyone who will listen "I'm a gonna build my own GAA. And my own BSPD. And I'm gonna do it in two years, in the same product because I'm just that good. And five years from now I'm gonna be delivering CFETs. And eight years from now I'm gonna shipping graphene chips. Just you wait. Burp. I'm a sleepy now."

Intel's particular style of clueless self-aggrandizement is a singularly terrible match for an environment of slow, patient (and unpredictable!) improvement. Again, for both its customers and Wall Street.

Tsmc today has ~10x value of Intc. Who has the better competence to handle the situation? The answer is quite obvious, as the resources available to them are vastly different. Tsmc can afford several teams devolping various strategies at the same time to hedge, while Intel does not even have money to finish new site construction. Does that mean Intel does not stand a chance, and just need to pack and go home? No.

Intel still has great talent, (limited) resources, and technical know-hows. I am rooting for Intel's resurgence.

Btw, if someone is winning, it seems that whatever it is planning to do is right; while a loser seems to do everything wrong. This is just human perception psychology.