Apple's tight integration and optimization has shown that there's room for multi-year leads in system efficiency just from tight hardware-software optimization.
Can you explain why this would be a such a big advantage for TSMC?According to TSMC:
Remember, N2 is nanosheets, which, unlike FinFETs, is not open source technology so this is really going to be a challenge for design and the supporting ecosystem which gives TSMC a very strong advantage. TSMC also mentioned what follows nanosheets which I found quite interesting. I’m sure we will hear more about this at IEDM 2023:
- Transistor architecture has evolved from planar to FinFET and is about to change again to nanosheet.
- Beyond nanosheet, TSMC sees vertically stacked NMOS and PMOS, known as CFET, as one of the key process architecture choices going forward.
- TSMC estimates the density gain would fall between 5 to 2X after factoring in routing and process complexity.
- Beyond CFET, TSMC made breakthroughs in low dimensional materials such as carbon nanotubes and 2D materials which could enable further dimensional and energy scaling.
Backside power delivery, AI remastering, pattern shaping technology, and probably several other complimentary techniques/approaches will also increase density.According to TSMC:
Remember, N2 is nanosheets, which, unlike FinFETs, is not open source technology so this is really going to be a challenge for design and the supporting ecosystem which gives TSMC a very strong advantage. TSMC also mentioned what follows nanosheets which I found quite interesting. I’m sure we will hear more about this at IEDM 2023:
- Transistor architecture has evolved from planar to FinFET and is about to change again to nanosheet.
- Beyond nanosheet, TSMC sees vertically stacked NMOS and PMOS, known as CFET, as one of the key process architecture choices going forward.
- TSMC estimates the density gain would fall between 5 to 2X after factoring in routing and process complexity.
- Beyond CFET, TSMC made breakthroughs in low dimensional materials such as carbon nanotubes and 2D materials which could enable further dimensional and energy scaling.
I agree with the thesis, but if one was to play devil's advocate would you not say that Samsung has all of the IP that most of their customers would use due to the overlap between LSI and the other mobile SOC designers? Of course the easy counter point would be missing out on the entirety of the HPC and the fact that not even LSI has a paper launched product on 3GAE. Either way I think it illustrates the point that especially in the case of Samsung, the IDM business can help with getting IP created for customers on new nodes (at the very least it seems like this has historically been the case even if it doesn't seem to be bearing fruit this time), as opposed to say UMC and GF which need to go out and build the ecosystem with their smaller than TSMC customer bases.
You don't think that Qualcomm won't use bits and pieces of ARM/Cadence/Synopsis IP that Samsung ports over for their own SOCs? If that truely is the case that feels like a big missed opportunity for Samsung to kill two birds with one stone and for Samsung's customers to accelerate TTM and minimize design costs due to redundant IP porting. But I don't really know all that much about the foundry IP/EDA space, if you say it doesn't make sense I trust your years of expense in this space more than my nonexistent experience in that vertical.
They don't. The ecosystem already exist and they are growing. Their MPWs allow this.
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