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What are TSM's Next Moves as Shrink Ends

Arthur Hanson

Well-known member
With shrink coming to an end, any thoughts or even speculation on what TSM's next move will be? TSM has always been forward-thinking, so they must have something in mind. A streamlined design process ecosystem? Layering and packaging? Larger chips like the huge Cerebras chip, silicon on fabric and chiplets? Lower costs to increase accessible market? any thoughts, comments or observations are appreciated.
 

count

Active member
I don't think there will be an end of shrink in the near term, but gains will more incremental. Chiplets appear to be the way forward, and with chiplets comes complexity in packaging. Lisa Su was talking about this recently, in how you need to not only think about the design of each chiplet, but how they all need to be packaged together. Given TSMCs strength in packaging I think this will be an area where they shine.
 

Jozo035

Member
3D. Multiple layers. Process will be aimed at efficiency with increased Tj. Performance gains will be achieved by 3D aware design (minimizing routing delay).

We will se it soon with AMD ZEN-3D.
 

Daniel Nenni

Admin
Staff member
People have been predicting an end to the semiconductor shrink for many years so I would not bet on it happening. Now that Intel seems to be back on track hopefully we will see more innovation from them. Remember, Intel brought us HKMG and FinFETs for better shrinkage. There has to be more semiconductor innovation coming, absolutely.

The Intel Innovation Conference is today, that may give us a clue.
 

Xebec

Member
People have been predicting an end to the semiconductor shrink for many years so I would not bet on it happening. Now that Intel seems to be back on track hopefully we will see more innovation from them. Remember, Intel brought us HKMG and FinFETs for better shrinkage. There has to be more semiconductor innovation coming, absolutely.

The Intel Innovation Conference is today, that may give us a clue.
The party does have to end some time though. There are several metrics that have been getting worse consistently with each node shrink:

- Total cost per fab
- R&D cost required per node
- Minimum theshold voltage (seems to have stopped decreasing)
- Clock speed increases for chips
- Node/transistor transistor performance gains (slowing down)
- Cost per wafer going up
- # of fabs that can afford leading edge nodes
- # of fabless companies that can afford designing chips on leading edge nodes
- SRAM and Analog size scaling

There's probably a chart of all of these that could predict reasonable points of no return with silicon technology..

Is there any metric that is accelerating recently (~ 10 years) that could point to a reversed trend of some kind?
 
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