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What are the historical and probable future node yields from Intel, Samsung, and TSMC?

fansink

Active member
Defect density was a common metric for fabs to share but they don't do it anymore. When Intel went into the foundry business last time they used outdated TSMC slides to discredit them saying a Pure-play Foundry could not go where an IDM Foundry could, the old foundry business model was dead, etc... TSMC quit sharing yield data after that. The problem you have is yield data changes and a slow ramping process really is the semiconductor walk of shame.

The TSMC Symposium is coming up in June. It will be interesting to see what they present. TSMC did not allow media originally but they do now so the amount of information is a lot less. A sign of the times for sure.
Thank you for that information Daniel, I did not originally appreciate the difficulty in finding or deriving this data, especially now that I understand many experts here have been down this same path.
 

IanD

Active member
It won't really help you directly estimate yield, but gives an idea of relatively how the companies are doing.

Intel: https://www.theverge.com/2022/1/26/22903138/intel-q4-2021-january-2022-earnings-best-year
30 million Tiger Lakes sold, margin over 50%

TSMC:
Using iPhone13 shipments as an indicator, obviously doing well: https://www.imore.com/iphone-shipments-hit-record-855-million-fourth-quarter-2021
Margins: ~38% (not just 5nm): https://investor.tsmc.com/chinese/e...12fc3ba28169ec091a86/4Q21ManagementReport.pdf

Samsung:
Galaxy S22 as indicator of Samsung 4nm, there have been delays: https://www.tomsguide.com/news/samsung-galaxy-s22-delays-heres-the-ship-date-for-each-model-now
Margins: 34% (all semiconductor) https://news.samsung.com/global/samsung-electronics-announces-fourth-quarter-and-fy-2021-results
Of course you're not really comparing like with like here; TSMC and Samsung are foundries who sell silicon to their customers, who then either sell on silicon to their customers (at a big margin to pay for their costs, can be up to 50% GM) or they use the silicon in their own products. Intel's 50% margin for Tiger Lake looks good, but actually it exposes that their fab yields and costs are worse than TSMC -- if you compare with AMD and work backwards from ASP, Intel's raw silicon cost is about 50% of ASP and AMDs (at the foundry) must be significantly less than that -- but the margin is split between TSMC and AMD.

This is why Intel Foundry Services are likely to have a problem; the fact that (certainly in the past) their processes cost more and yielded worse than TSMC was hidden by the fact that Intel were selling end product, not foundry silicon -- and the Intel fabs and processes being biased towards performance and away from cost and yield was the right thing for Intel. Once they step into the foundry business this no longer works; to compete with TSMC their processes will need to prioritise cost and especially yield not just performance, and this needs a change in approach away from the "traditional" Intel one.

And since TSMC are absolutely the kings of yield, I suspect they'll eat Intel's lunch...
 

Fred Chen

Moderator
Yes, to clarify, TSMC gross margins were also over 50%, and AMD just shy of 50%, so Intel should have had over 75% gross margin if their silicon processing cost was same as TSMC's. That not being the case, it's more expensive, including yields. But AMD processor volume from TSMC should hopefully also be over 100 million.
 
Last edited:

Scotten Jones

Moderator
When you talk about defect density you have to keep in mind that it varies by defect model, e.g. Murphy defect density isn’t the same as Seeds, etc.

I have decades of defect density data but it isn’t something I am going to share here and I have had to put a lot of work into calibrating it all into the same defect model.

The following are some recent yield experiences: The Qualcomm Snapdragon 8 has been reported to be yielding only ~30% in Samsung N4, it supposedly also yielded ~70% in TSMC N4. Samsung N3 is supppsed to be yielding ~20% at best.
 

IanD

Active member
When you talk about defect density you have to keep in mind that it varies by defect model, e.g. Murphy defect density isn’t the same as Seeds, etc.

I have decades of defect density data but it isn’t something I am going to share here and I have had to put a lot of work into calibrating it all into the same defect model.

The following are some recent yield experiences: The Qualcomm Snapdragon 8 has been reported to be yielding only ~30% in Samsung N4, it supposedly also yielded ~70% in TSMC N4. Samsung N3 is supppsed to be yielding ~20% at best.

From the Intel vs. TSMC cost/margin numbers in posts above, it seems likely the Intel Foundry Service process costs/yields are much closer to Samsung than TSMC -- fine for vertically integrated products like x86 CPUs, but not for ASICs.

This doesn't bode well for IFS trying to compete with TSMC, not to mention the comparative lack of design ecosystem which is a big TSMC advantage and where IFS will be even worse off than Samsung.

Unless IFS can compete with TSMC on yield and cost -- and bring up a decent IP ecosystem -- all Pat Gelsinger's foundry ambitions are likely to come to nothing, like they did last time Intel tried the same thing a few years back.

Intel might be able to get their in-house processes up to speed for x86 CPUs where they can can hide the cost/yield problems, but they're starting from a long way behind TSMC especially with EUV experience and ASML stepper availability -- it will be a big uphill task to catch up with TSMC, and an even bigger one to overtake them as Gelsinger is claiming.
 

fansink

Active member
From the Intel vs. TSMC cost/margin numbers in posts above, it seems likely the Intel Foundry Service process costs/yields are much closer to Samsung than TSMC -- fine for vertically integrated products like x86 CPUs, but not for ASICs.

This doesn't bode well for IFS trying to compete with TSMC, not to mention the comparative lack of design ecosystem which is a big TSMC advantage and where IFS will be even worse off than Samsung.

Unless IFS can compete with TSMC on yield and cost -- and bring up a decent IP ecosystem -- all Pat Gelsinger's foundry ambitions are likely to come to nothing, like they did last time Intel tried the same thing a few years back.

Intel might be able to get their in-house processes up to speed for x86 CPUs where they can can hide the cost/yield problems, but they're starting from a long way behind TSMC especially with EUV experience and ASML stepper availability -- it will be a big uphill task to catch up with TSMC, and an even bigger one to overtake them as Gelsinger is claiming.

Intel’s IDM enjoys using almost all live (even limping) chips, by lowering voltage and frequency (binning) of those less than par chips. They even use chips that can have some features turned off (due to defect).

Samsung’s IDM likely enjoys similar binning utilization, perhaps to a lesser degree than Intel.

As a result, their stated yield numbers cannot easily be correlated to defect density, if at all.
 

IanD

Active member
Intel’s IDM enjoys using almost all live (even limping) chips, by lowering voltage and frequency (binning) of those less than par chips. They even use chips that can have some features turned off (due to defect).

Samsung’s IDM likely enjoys similar binning utilization, perhaps to a lesser degree than Intel.

As a result, their stated yield numbers cannot easily be correlated to defect density, if at all.
And their yield for foundry business might be even lower than estimated above. Selling your own multiple-binned chips as different products at very different price points can hide an *awful* lot of fab yield/cost sins... ;-)
 

fansink

Active member
And their yield for foundry business might be even lower than estimated above. Selling your own multiple-binned chips as different products at very different price points can hide an *awful* lot of fab yield/cost sins... ;-)

You got that right !!!
 

hist78

Well-known member
Intel’s IDM enjoys using almost all live (even limping) chips, by lowering voltage and frequency (binning) of those less than par chips. They even use chips that can have some features turned off (due to defect).

Samsung’s IDM likely enjoys similar binning utilization, perhaps to a lesser degree than Intel.

As a result, their stated yield numbers cannot easily be correlated to defect density, if at all.
I always wonder how Apple uses the same A* SoC across multiple models within the same iPhone generation? For example no matter which model of iPhone 13 you purchased, they all have the same A15 Bionic inside.

Does that mean TSMC/Apple are capable to make chips to have uniform performance or they just dumped the substandard ones?
 

fansink

Active member
I always wonder how Apple uses the same A* SoC across multiple models within the same iPhone generation? For example no matter which model of iPhone 13 you purchased, they all have the same A15 Bionic inside.

Does that mean TSMC/Apple are capable to make chips to have uniform performance or they just dumped the substandard ones?

Probably more binning.
 

lilo777

Active member
I always wonder how Apple uses the same A* SoC across multiple models within the same iPhone generation? For example no matter which model of iPhone 13 you purchased, they all have the same A15 Bionic inside.

Does that mean TSMC/Apple are capable to make chips to have uniform performance or they just dumped the substandard ones?
Why is that confusing? Different models have the same processor but different displays. They use the same processor to save on processor design. Reportedly, for the next iPhone line they will be using different processors (old and new ones) because they can't procure enough of the new chips from TSMC (or, maybe, the new ones are too expensive to use on cheaper phones).
 

fansink

Active member
Why is that confusing? Different models have the same processor but different displays. They use the same processor to save on processor design. Reportedly, for the next iPhone line they will be using different processors (old and new ones) because they can't procure enough of the new chips from TSMC (or, maybe, the new ones are too expensive to use on cheaper phones).

I don't think anyone is confused, we all know that foundries have been binning for decades (since the 80's).
 

lilo777

Active member
I don't think anyone is confused, we all know that foundries have been binning for decades (since the 80's).
I do not think Apple does any binning for phone processors. They advertise the fact that all iPhones (same generation) have the same processor.
 
M

mgoldsmith1979

Guest
I always wonder how Apple uses the same A* SoC across multiple models within the same iPhone generation? For example no matter which model of iPhone 13 you purchased, they all have the same A15 Bionic inside.
Does that mean TSMC/Apple are capable to make chips to have uniform performance or they just dumped the substandard ones?
Apple products do occasionally disable a core to recover from defects (eg: A12X only utilized 7 of 8 GPU cores, while A12"Z" enabled all 8), though Apple does not advertise a specific core frequency on their products in order to see if they are also doing V-F / fast-slow distribution part bins as well. Very likely they also include redundancy in their SRAM macros for repair as well, given how much of their die area is SRAM.
The parts are labeled with some MPN SKU differences though not in the formal part number. There are strings of letters between the "APLnnnn" and the production date code that could be used to identify part bins, but it isn't disclosed what that means. In the past, they would claim different Fmax for the same parts used in iPod Touch vs iPhone or iPad, and they might assign specific part bins to specific products based on the thermal performance, but from examining the in-market part labels I have no idea how they would track that.
Another explanation is they close timing at the slow corner, and any fast parts they just undervolt to get consistent performance across the corner distribution (at the expense of minor variation in end-product battery life). Anything that fails to pass the slow corner timing gets discarded.
 

IanD

Active member
Apple products do occasionally disable a core to recover from defects (eg: A12X only utilized 7 of 8 GPU cores, while A12"Z" enabled all 8), though Apple does not advertise a specific core frequency on their products in order to see if they are also doing V-F / fast-slow distribution part bins as well. Very likely they also include redundancy in their SRAM macros for repair as well, given how much of their die area is SRAM.
The parts are labeled with some MPN SKU differences though not in the formal part number. There are strings of letters between the "APLnnnn" and the production date code that could be used to identify part bins, but it isn't disclosed what that means. In the past, they would claim different Fmax for the same parts used in iPod Touch vs iPhone or iPad, and they might assign specific part bins to specific products based on the thermal performance, but from examining the in-market part labels I have no idea how they would track that.
Another explanation is they close timing at the slow corner, and any fast parts they just undervolt to get consistent performance across the corner distribution (at the expense of minor variation in end-product battery life). Anything that fails to pass the slow corner timing gets discarded.

Since everything in the phone is under Apple's control, they can take this even further -- raise voltage for slow chips to increase speed (at the expense of higher power) and lower it for fast chips to save power. This means that all devices can run at the same headline clock speeds, but some take more power than others to do it -- but in fact it might tighten up the power distribution as well because fast chips have more leakage power and slow chips have less, which is the opposite trend. This is just an extension of DVFS which is used intensively anyway, so the hardware and software needed to do it will already exist.
 

hist78

Well-known member
Since everything in the phone is under Apple's control, they can take this even further -- raise voltage for slow chips to increase speed (at the expense of higher power) and lower it for fast chips to save power. This means that all devices can run at the same headline clock speeds, but some take more power than others to do it -- but in fact it might tighten up the power distribution as well because fast chips have more leakage power and slow chips have less, which is the opposite trend. This is just an extension of DVFS which is used intensively anyway, so the hardware and software needed to do it will already exist.
In order to make it work as you described, does that mean there's a relatively small varience among the same generation of Apple A* SoC?

Apple sold about 239 million units multiple models of iPhones in 2021. To standardize a huge number of iPhone performance and power usage for a particular model has to be manageable and cost effective.
 

IanD

Active member
In order to make it work as you described, does that mean there's a relatively small varience among the same generation of Apple A* SoC?

Apple sold about 239 million units multiple models of iPhones in 2021. To standardize a huge number of iPhone performance and power usage for a particular model has to be manageable and cost effective.

The device variance is whatever it is coming out of the fab coupled with Apple's acceptance criteria for rejecting too-slow or too-fast wafers/chips. DVFS like I described isn't difficult to do if you have control over the power supplies, which Apple certainly have in their phones.

As I said, it can not only be used to reduce the speed variation, if the chip is designed to work this way from the beginning (which needs custom libraries and toolchain, not exactly a problem for Apple) it can also reduce the power variation, "fast" chips run at lower voltage with lower dynamic power but higher leakage power, "slow" chips run at higher voltage with higher dynamic power but lower leakage power.

If the chip and system are designed to work this way (with on-chip speed/power sensors) there's no added cost or management complexity, at least not per-unit -- there's some extra work up front but the cost of this is spread over millions of phones.

We do this all the time, so I'd be amazed if Apple don't because the benefits are huge...
 

Xebec

Active member
When you talk about defect density you have to keep in mind that it varies by defect model, e.g. Murphy defect density isn’t the same as Seeds, etc.

I have decades of defect density data but it isn’t something I am going to share here and I have had to put a lot of work into calibrating it all into the same defect model.

The following are some recent yield experiences: The Qualcomm Snapdragon 8 has been reported to be yielding only ~30% in Samsung N4, it supposedly also yielded ~70% in TSMC N4. Samsung N3 is supppsed to be yielding ~20% at best.
Scotten - just for my education can you define yield in this context ? Is it works at all, works at a given frequency, leakage, power? (Assuming the latter).

And could yield in this example change much with "some" relaxation of those previous parameters?
 

Scotten Jones

Moderator
Scotten - just for my education can you define yield in this context ? Is it works at all, works at a given frequency, leakage, power? (Assuming the latter).

And could yield in this example change much with "some" relaxation of those previous parameters?
Generally speaking this is the electrical yield at wafer sort and it is the percentage of die that meet a set of electrical specs. If you get defect density from a foundry it will typically be extracted from a test chip once again to the process specs. Yes if you relax the specs the yield will go up.
 
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