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Wafer Capacity by Feature Size Shows Rapid Growth at <10nm

Daniel Nenni

Admin
Staff member
Cellphone and graphics processors drive demand for leading edge processes

Leading-edge processes (<28nm) took over as the largest portion in terms of monthly installed capacity available in 2015. By the end of 2019, <28nm capacity is forecast to represent about 49% of the IC industry’s total capacity, based on information in IC Insights’ Global Wafer Capacity 2019-2023 report. At the very leading edge, <10nm processes are now in volume production and are forecast to represent 5% of worldwide capacity in 2019. The share of <10nm capacity is forecast to jump to 25% and become the largest capacity segment by 2023 (Figure 1).

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Figure 1
South Korea (Samsung) and Taiwan (TSMC) are currently the only two regions with fabs processing what are being called <10nm processes. South Korea and Japan both have large shares of capacity in the <20nm – ≥10nm segment, with the vast majority of it being used to produce NAND flash (equivalent feature size) and DRAM, but also some for advanced logic and application processors built with 14nm, 10nm, or 8/7nm technology. Taiwan also has a large share of the <20nm – ≥10nm capacity, with roughly half of it being for foundry services and the other half for DRAM production.

Trends at the leading edge have been changing and the industry is departing from historical “norms.” The gray area of what constitutes a generation and how to measure the minimum process geometry gets more difficult every year. Therefore, any assumptions made regarding the wafer fab capacity of new process technologies can have a big impact on the forecast for wafer capacity by minimum feature size.

Other findings from the Global Wafer Capacity 2019-2023 report include,

• South Korea remains significantly more leading-edge (i.e., <28nm) focused than the other regions or countries. Given Samsung and SK Hynix’s emphasis on high-density DRAM and flash memory products, it is not a surprise that the country has the highest concentration of wafer capacity dedicated to the leading-edge processes.

• When only the most advanced processes (<20nm) are considered, South Korea also has the largest share of its total capacity dedicated to these processes than any other region. For logic-based processes, Taiwan, North America, and South Korea have the highest concentrations at the leading edge.

• Current leading-edge (<28nm) capacity in China is completely owned and controlled by foreign companies, namely Samsung, SK Hynix, Intel, and TSMC.

• Taiwan has the largest shares of capacity in the <65nm – ≥28nm and <0.2µ – ≥65nm technology segments. Nevertheless, the 28nm, 45/40nm, and 65nm generations continue to generate significant business volumes for foundries like TSMC and UMC.

Report Details: Global Wafer Capacity 2019-2023
IC Insights’ Global Wafer Capacity 2019-2023—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity report assesses the IC industry’s capacity by wafer size, minimum process geometry, technology type, geographic region, and device type through 2023. The report includes detailed profiles of the companies with the greatest fab capacity and gives comprehensive specifications on existing wafer fab facilities. Global Wafer Capacity 2019-2023 is priced at $4,890 for an individual user license. A multi-user worldwide corporate license is available for $7,590.

To review additional information about IC Insights’ new and existing market research reports and services please visit our website: www.icinsights.com.

PDF Version of This Bulletin
A PDF version of this Research Bulletin can be downloaded from our website at http://www.icinsights.com/news/bulletins/
 

Arthur Hanson

Active member
Any thoughts on the type of capacity needed for Crossbar or 3dXpoint memory? Are these processes radically different from existing processes since they use an extensive layered grid layout? Any insights on the processes for these types of memory would be appreciated. Also are the processes related to MEMS, although at larger nodes advancing at the same rate as other processes? Will MEMS ever be built on the same die or always be a separate device tightly packaged with the support semis needed? Thanks
 

mfrankel

New member
In term of $revenues per technology TSMC has published thie pic showing that 7nm generates in Q3 2019 27%!!

To be compared with installed WW capacity of 5% on 7nm... TSMC is really at the leading edge!!
Since 7 nm represents 27% of revenue and 5% of capacity, does it mean that it is A LOT more expensive than large geometries?
Does anyone have data on current relative costs?
 
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