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VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

Daniel Nenni

Staff member
Tom Dillinger did an excellent review of his new book in the 27 minute webinar (replay):

If you have questions for Tom post them here so we can do a follow-up Q&A.
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I'm significantly unqualified to say much on this topic, especially since Tom's understanding of these topics, especially around VLSI implementation, is massively deeper than mine. That said, from my limited perspective the book covers all the advanced topics that I know to be relevant and current today. Given Tom's hands-on and management experience across all aspects of VLSI design, at IBM and elsewhere, I'm sure this will be a valuable resource for graduate programs.

Daniel Payne

Tom, very comprehensive topics in your book with 700+ pages. I look forward to added content on topics like: packaging, 2.5D, 3D chips, chiplets, IBIS modeling.

Daniel Nenni

Staff member
While the webinar is targeting microelectronics students with an up-to-date description of SoC design flows and methodology options, professional engineers should view this as well. You should also take a look at Tom's FinFET series which brought FinFET's to SemiWiki in April of 2012:


Randy Smith

Tom, great job of covering such a large field of technology. I guess it gets more blurry all the time where system design ends and VLSI design starts. Maybe these did not show up in the overview, but I was wonder if you cover these topics in the text: High-level synthesis (HLS), HW/SW co-design, and IP sourcing and selection. Thanks, again. I hope your books allows students to get ready to be productive in industry more quickly.

Thanks for your comments and questions! Alas, due to limitations on the length of the text, some topics only received a brief introduction.

- high-level synthesis (HLS)

The text does go into some detail on the distinctions between sequential and RTL coding styles in current hardware description languages (Verilog, VHDL). Yet, the chapter on Logic Synthesis is more focused on "physical synthesis" and how designers provide input constraints for timing and power optimizations. There's not really any detail on other HDL options (e.g., "synthesizable C" semantics) or the HLS optimization algorithms used for resource allocation and scheduling.

- HW/SW co-design

This topic is also not covered in a lot of detail, other than the chapter sections describing simulation acceleration platforms (i.e., emulation, prototyping) as a means for SW bring-up on a system model. (There's a brief discussion on development of a separate "performance model", which provides throughput estimates on software workloads; this model is subsequently validated against more detailed functional simulation results.)

- IP sourcing/selection

Yes, the evaluation criteria for (hard/firm/soft) IP selection is covered pretty thoroughly. The breadth of models associated with IP delivery is described in detail. The assessment of the power, performance, area, reliability, and licensing cost is also highlighted.

HTH. Thanks again!

Tom D.


New member
Hi Tom, it is a very good book covering many topics in the field. We decided to use this book in our VLSI course. I bought from Amazon and asked Pearson if there are any supporting materials to use in lectures such as ppt files. However they could not find it. Since it is a new book this is understandable. I want to ask if you have such course materials. I would appreciate it very much if you can provide.



Thanks for the comments about the book!

Pearson Publishing recently added a set of presentation slides to the web site for the book.

I created a slide for each figure in the book, with supporting comments. The slides for each chapter are compressed into a .zip file and available for download from Pearson:

When you click on the .zip file for download, Pearson will ask you to create an Educator account. If you have any questions, or if I can assist in any way, please do not hesitate to let me know. Any and all feedback on the slides or the text material would be most welcome. Thanks again!

Tom D.