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VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

I'm significantly unqualified to say much on this topic, especially since Tom's understanding of these topics, especially around VLSI implementation, is massively deeper than mine. That said, from my limited perspective the book covers all the advanced topics that I know to be relevant and current today. Given Tom's hands-on and management experience across all aspects of VLSI design, at IBM and elsewhere, I'm sure this will be a valuable resource for graduate programs.
 

Daniel Payne

Moderator
Tom, very comprehensive topics in your book with 700+ pages. I look forward to added content on topics like: packaging, 2.5D, 3D chips, chiplets, IBIS modeling.
 

Daniel Nenni

Admin
Staff member
While the webinar is targeting microelectronics students with an up-to-date description of SoC design flows and methodology options, professional engineers should view this as well. You should also take a look at Tom's FinFET series which brought FinFET's to SemiWiki in April of 2012:

 

Randy Smith

Moderator
Tom, great job of covering such a large field of technology. I guess it gets more blurry all the time where system design ends and VLSI design starts. Maybe these did not show up in the overview, but I was wonder if you cover these topics in the text: High-level synthesis (HLS), HW/SW co-design, and IP sourcing and selection. Thanks, again. I hope your books allows students to get ready to be productive in industry more quickly.
 

Tom Dillinger

Moderator
Randy:

Thanks for your comments and questions! Alas, due to limitations on the length of the text, some topics only received a brief introduction.

- high-level synthesis (HLS)

The text does go into some detail on the distinctions between sequential and RTL coding styles in current hardware description languages (Verilog, VHDL). Yet, the chapter on Logic Synthesis is more focused on "physical synthesis" and how designers provide input constraints for timing and power optimizations. There's not really any detail on other HDL options (e.g., "synthesizable C" semantics) or the HLS optimization algorithms used for resource allocation and scheduling.

- HW/SW co-design

This topic is also not covered in a lot of detail, other than the chapter sections describing simulation acceleration platforms (i.e., emulation, prototyping) as a means for SW bring-up on a system model. (There's a brief discussion on development of a separate "performance model", which provides throughput estimates on software workloads; this model is subsequently validated against more detailed functional simulation results.)

- IP sourcing/selection

Yes, the evaluation criteria for (hard/firm/soft) IP selection is covered pretty thoroughly. The breadth of models associated with IP delivery is described in detail. The assessment of the power, performance, area, reliability, and licensing cost is also highlighted.

HTH. Thanks again!

Tom D.
 
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