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Video and Presentation material of Intel 2020 Architecture Day

Fred Chen

Moderator
Slide 17 says 0.51x scaling, is this area scaling or direct pitch scaling?

I just read this paper: https://ieeexplore.ieee.org/document/8430489, there they claimed M1 36 nm pitch is 0.51 x scaling from 14nm M1 pitch (70 nm) while M0 was 0.71x from 56 nm pitch. 0.51x scaling applied to M0 there would be 28-29 nm. Then for sure, both M0 and M1 need SAQP.

If it is 0.51 x area scaling instead of pitch, then M0 and M1 each get 0.71x pitch scaling, M0 goes to 40nm, M1 goes to 50 nm, these are accessible by SADP instead of SAQP.

For reference:

Intel 14nm:
Intel 10nm: https://people.eecs.berkeley.edu/~pister/140sp20/resources/Intel 10nm IEDM2017.pdf
 
Last edited:

Daniel Nenni

Admin
Staff member
 

Portland

Member
Intel looks strong for now. The one thing is architecture is more essential than node size or enhancements. To do both well was becoming too big for a single company before covid.
 

Daniel Nenni

Admin
Staff member
Agreed. The people who matter (systems companies) know which chips are best without reading about them on rumor sites. I was on a call yesterday with system integrators and the consensus was that Intel is back in the lead, absolutely. But it is nice to have a second option (AMD) to keep prices reasonable and technology moving.

Intel looks strong for now. The one thing is architecture is more essential than node size or enhancements. To do both well was becoming too big for a single company before covid.
 

hskuo

Member
From this event, I was surprised there is no new stuff in process technology. intel even did not show his process roadmap with code name and timeline which was typically observed in their past technology events. Maybe it is the reason why it was called Architecture Day. As all we know, Samsung and tsmc are talking about Nanosheet in their 3GAE/3GAP(MBCFET) and N2(Likely to be Nanosheet) for next 2-5 years, respectively. What we found in this intel event? Super"Fin". Super"MIM". Which are not so new in this industry. Someone even called it a "CIP" for process. Did we hear any comment about this new process "architecture" called GAA/Nanosheet? I did not hear it. If there were two horses for intel moving forward in the past, I would say one is saddled off now and unbalance could happen. Competition is critical for industry moving forward. The criterion of being #1 is you win over #2 and be acceptable by your customers. Good luck for tier 1 process technology leaders.
 

lilo777

Member
From this event, I was surprised there is no new stuff in process technology. intel even did not show his process roadmap with code name and timeline which was typically observed in their past technology events. Maybe it is the reason why it was called Architecture Day. As all we know, Samsung and tsmc are talking about Nanosheet in their 3GAE/3GAP(MBCFET) and N2(Likely to be Nanosheet) for next 2-5 years, respectively. What we found in this intel event? Super"Fin". Super"MIM". Which are not so new in this industry. Someone even called it a "CIP" for process. Did we hear any comment about this new process "architecture" called GAA/Nanosheet? I did not hear it. If there were two horses for intel moving forward in the past, I would say one is saddled off now and unbalance could happen. Competition is critical for industry moving forward. The criterion of being #1 is you win over #2 and be acceptable by your customers. Good luck for tier 1 process technology leaders.
TSMC and Saamsung have to advertise their process roadmaps to attract the customers. Intel does not have customers for their process. Obviously there is a big difference between the future plans and what's available now. I am curious if TSMC has SuperFin or something similar in current process(es).
 
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