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TSMC Expands Advanced Technology Leadership with N4P Process

Daniel Nenni

Admin
Staff member
N4P Extends the Performance, Power Efficiency and Density Leadership of the 5nm Platform

Hsinchu, Taiwan, R.O.C., Oct. 26, 2021 - TSMC (TWSE: 2330, NYSE: TSM) today introduced its N4P process, a performance-focused enhancement of the 5-nanometer technology platform. N4P joins the industry’s most advanced and extensive portfolio of leading-edge technology processes. With N5, N4, N3 and the latest addition of N4P, TSMC customers will have multiple and compelling choices for power, performance, area, and cost for its products.

As the third major enhancement of TSMC’s 5nm family, N4P will deliver an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density. In addition, N4P lowers process complexity and improves wafer cycle time by reducing the number of masks. N4P demonstrates TSMC’s pursuit and investment in continuous improvement of our process technologies.

TSMC customers often invest precious resources to develop new IP, architectures, and other innovations for their products. The N4P process was designed for an easy migration of 5nm platform-based products, which enables customers to not only better maximize their investment but will also deliver faster and more power efficient refreshes to their N5 products.

N4P designs will be well-supported by TSMC’s comprehensive design ecosystem for silicon IP and EDA. With TSMC and its Open Innovation Platform® partners helping to accelerate the product development cycle, the first products based on N4P technology are expected to tape out by the second half of 2022.

“With N4P, TSMC strengthens our portfolio of advanced logic semiconductor technologies, each with its unique blend of performance, power efficiency and cost. N4P was optimized to provide a further enhanced advanced technology platform for both HPC and mobile applications,” said Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC. “Between all the variants of N5, N4 and N3 technologies, our customers will have the ultimate flexibility and unmatched choice of the best mix of attributes for their products.”

TSMC Spokesperson​

Wendell Huang
Vice President & Chief Financial Officer
Tel:886-3-5055901

TSMC Deputy Spokesperson​

Nina Kao
Public Relations Department
Tel:886-3-5636688 Ext.7125036
 

Xebec

Member
What does "performance boost" mean exactly in this case ? Does it mean higher clock speeds possible at a "safe voltage" or maybe at the same voltage as a previous node ?
 
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