TSMC commits to nanosheets at 2nm

[prime007]

EE Times reports that TSMC has now publicly confirmed that they will be using nanosheets at 2nm starting in 2025. They also gave a quick preview of TSMC roadmap for the next few years as well as provide some color on the competitive foundry market.

Source: https://www.eetimes.com/tsmc-commits-to-nanosheet-technology-at-2-nm-node/

 

[Xebec]

Is the key

Nanosheets = MBCFET = RibbonFET ? while all are effectively GAA?

 

[Fred Chen]

I wonder how much it will help reduce gate pitch.

 

[Daniel Nenni]

EE Times reports that TSMC has now publicly confirmed that they will be using nanosheets at 2nm starting in 2025. They also gave a quick preview of TSMC roadmap for the next few years as well as provide some color on the competitive foundry market.

Source: https://www.eetimes.com/tsmc-commits-to-nanosheet-technology-at-2-nm-node/

TSMC did not publicly confirm it, this is a leaked story. I would not waste your time on it. We will be writing about it in more detail the day of and the days following the Technical Symposium next week.

I really expect better from EETimes, very disappointing.

 

[hskuo]

I wonder how much it will help reduce gate pitch.

I guess there will be no further DR shrink between 3nm and 2nm. Like the case in TSM 20nm t0 16nm, which changed transistor architecture from planar to finFET.

 

[Daniel Nenni]

I think 3nm will be the biggest and longest node for TSMC with the most variants. Nanosheets/GAA still has a ways to go in regards to density and performance improvements, certainly not the node PPA deltas we are used to. Nanosheets do have power advantages and we will be writing more about that. Power is certainly important but with AI driving semiconductors, performance will always be at a premium, my opinion.