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TSMC 5nm+ volume production Q420

kh812000

New member
TSMC is on a roll if they really start 5nm+ production in Q4.... just in time for new mobile phone launches at CES/WMC.
Supposedly AMD will be a fast follower on this node as well which bodes poorly for Intel's process game.
===============
Digitimes Article

TSMC to move 5nm Plus process to volume production in 4Q20
Monica Chen, Taipei; Jessie Shen, DIGITIMES
Thursday 28 May 2020

TSMC is expected to kick off volume production of chips manufactured on an enhanced version of its 5nm FinFET process, dubbed tentatively 5nm Plus, in the fourth quarter of 2020, according to sources familiar with the matter.
 
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Daniel Nenni

Admin
Staff member
Apple will have N5 in the iProducts this year for sure. Some say the iPhone 12 announcement will be delayed but I certainly hope not. I need a new iPhone.

Ignoring the media reports , N5+ should enter risk production in Q4 2020 and in Apple iProducts in Q4 2021. I asked Scott Jones for a quick updated comparison of N5 and N5+ just to see what the differences are at this point in time.


TSMC is on a roll if they really starts 5nm+ production in Q4. Seems like just in time for new mobile launches at CES/WMC?
Supposedly AMD will be a fast follower on this node as well which bodes ill for Intel's process game.
===============
Digitimes Article

TSMC to move 5nm Plus process to volume production in 4Q20
Monica Chen, Taipei; Jessie Shen, DIGITIMES
Thursday 28 May 2020

TSMC is expected to kick off volume production of chips manufactured on an enhanced version of its 5nm FinFET process, dubbed tentatively 5nm Plus, in the fourth quarter of 2020, according to sources familiar with the matter.
 

Portland

Member
Whatever. I'm sure 5+ is better but is it really significant. Amd? Intel was the company with the killer instinct.
 

count

Active member
Whatever. I'm sure 5+ is better but is it really significant. Amd? Intel was the company with the killer instinct.
Intel has so far managed to hold on to majority share by leveraging it's market power, but it gets harder and harder to do as the performance gap widens. If Zen 3 ends up being on 5nm+ as per some recent rumors (https://www.notebookcheck.net/AMD-s...-scheduled-to-launch-in-Q4-2020.466975.0.html), they could have as much as a 2x performance lead on Intel. When the performance lead is maybe 25%, I think most customers will still stick to their existing relationships with the brand they know. But no-one is going to be able to ignore a 2x difference in performance.
 

Daniel Nenni

Admin
Staff member
From what I understand: N5+ is 7% better performance or 15% lower power. Same design rules, some kind of enhanced high mobility channel (pFET) and other process tweaks.

Whatever. I'm sure 5+ is better but is it really significant. Amd? Intel was the company with the killer instinct.
 

kh812000

New member
7% better perf or 15% lower power is quite large for N5 to N5+.
If design rules are truly identical its going to be seamless to quickly migrate over from N5 to N5+....
 

Daniel Nenni

Admin
Staff member
Similar to N16/N12, not quite seamless but there is no redesign. Example: there will be some additional simulation/characterization work to be done for the IP. Same design rules but they will be optimized for better power/performance now that the HVM yield is mastered. It is my understanding that N3 will use the same fab so your N5 design will have a much longer life than others.

7% better perf or 15% lower power is quite large for N5 to N5+.
If design rules are truly identical its going to be seamless to quickly migrate over from N5 to N5+....
 
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hskuo

Member
From what I understand: N5+ is 7% better performance or 15% lower power. Same design rules, some kind of enhanced high mobility channel (pFET) and other process tweaks.
It will be quite busy to see tsmc N5, N6 and N5+ all around in 2020Q4. Will tsmc rename them to like N5, N5HPC, N6FFC?
 

Daniel Nenni

Admin
Staff member
It will be quite busy to see tsmc N5, N6 and N5+ all around in 2020Q4. Will tsmc rename them to like N5, N5HPC, N6FFC?
I don't think it is too busy. TSMC N10, N7, N7+, and N6 are the same fab. N5, N5+, and probably N3 will be the same fab. The important point to note is that EUV is improving so the better process will be in the N5 fabs. So I think customers will move faster to N5 to get the improved EUV and not just the power/performance improvements. Sound reasonable?
 

hskuo

Member
I don't think it is too busy. TSMC N10, N7, N7+, and N6 are the same fab. N5, N5+, and probably N3 will be the same fab. The important point to note is that EUV is improving so the better process will be in the N5 fabs. So I think customers will move faster to N5 to get the improved EUV and not just the power/performance improvements. Sound reasonable?
From production point of view, you are right because they are produced in the same fab sites using the same tools. But from technology development point of view, each tech node takes time for validation and transferring from RD sites to HVM sites. From customer point of view, cost effective nodes are the one to be chosen. If 3 new nodes are promoted at the same period, it is indeed quite busy and labor intensive.
 

count

Active member
From production point of view, you are right because they are produced in the same fab sites using the same tools. But from technology development point of view, each tech node takes time for validation and transferring from RD sites to HVM sites. From customer point of view, cost effective nodes are the one to be chosen. If 3 new nodes are promoted at the same period, it is indeed quite busy and labor intensive.
These nodes will target and be promoted to different customers, and in many cases, the nodes exist because a specific large customer asked for it. If I'm a mobile chip customer, TSMC will be promoting a different node to me than if I was a HPC customer, or if I'm an embedded customer. If I'm Apple or NVidia, I may have my very own node that I have exclusive access to for the next year. As long as TSMC delivers the node that I care about, I'm happy.

TSMC has no problem delivering and managing several nodes at the same time, that's core to their business.
 

Daniel Nenni

Admin
Staff member
Ever since Apple joined at 20nm TSMC has been putting out a new process variations every year so nothing has changed. And now with AMD in the inner circle TSMC will continue to dominate the leading edge, my opinion. It is a shame the TSMC symposiums are cancelled this year. It really is better to hear it from them directly in front of hundreds of customers. This media "leaking" stuff is nonsense.

From production point of view, you are right because they are produced in the same fab sites using the same tools. But from technology development point of view, each tech node takes time for validation and transferring from RD sites to HVM sites. From customer point of view, cost effective nodes are the one to be chosen. If 3 new nodes are promoted at the same period, it is indeed quite busy and labor intensive.
 

IanD

Member
N5 and N5+ design rules and layouts are identical, you get a bit more speed (+7%) at the same voltage or lower power (-15%) for the same speed (by lowering Vdd), and this comes "for free" in IP being designed today -- all you do is switch to the N5+ models and libraries. Of course "for free" isn't a phrase often used when talking about 5nm, "ridiculously expensive" is much more common...
 

Daniel Nenni

Admin
Staff member
I spoke too soon:


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Ever since Apple joined at 20nm TSMC has been putting out a new process variations every year so nothing has changed. And now with AMD in the inner circle TSMC will continue to dominate the leading edge, my opinion. It is a shame the TSMC symposiums are cancelled this year. It really is better to hear it from them directly in front of hundreds of customers. This media "leaking" stuff is nonsense.
 
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IanD

Member
It's not quite comparing like for like, but to show that processes are still delivering power/speed improvements, the total power saving from N7 to N5+ (if you run at the same speed but with lower Vdd, and take advantage of new process features like ELVT transistors) is about 50% according to TSMC figures (which benchmarks agree with):

N7 ==> N5 : 30% power saving (x0.7)
Adding N5 ELVT transistors (not available in N7) : 15% power saving (x0.85)
N5 ==> N5+ : 15% power saving (x0.85)

Unfortunately the product of power consumption and NRE cost is roughly constant... :-(
 
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