No clue how it was formulated. Maybe they give some hint during the IDM2.0 webinar, but I don't feel like rewatching it.
My gut says without IFS... no. One reason for this assessment is that back in the 2000-2016 period intel's tech lead vs ROW was even bigger than the lead TSMC had over intel in the 2018-2022 time period. Besides just the performance implication of that lead; there was also a HUGE cost lead that made intel more competitive than they would have otherwise been (as evidenced by Pat's process tech going out like the tide and exposing the design side comment). Considering that the economic benefits for new nodes are softening and that intel doesn't appear to be opening up a multi node lead like they used to have, design must create value AND cost competitive products to raise both units shipped and margins. IMO folks like TSMC, AMD, and NVIDIA are too good for either the manufacturing or the design sides to single handedly carry the other half of the firm back to intel's historical market domination.
Besides the marketshare angle, there is another factor that I see as acting as both a head and tailwind to manufacturing volume... Chiplets. Intel has talked plenty about how converting old fabs to new processes robbed them of the ability to subsidise new nodes with the old ones. In an IDM1.0 world disaggregating designs can allow for longer tails on these processes. However you also reduce the amount of wafers you need from the new process. MTL is an excellent example of this. MTL compute die looks way smaller than the equivalent ADL mobile dies. As a result intel needs fewer wafer starts for the same product demand (assuming iso yield and that dpw scales linearly with the die size). The way I see it going disag means you are in effect trading your scale for a faster capacity ramp and a longer tail. As a side note: I think this is one of the neat things about Samsung. Their IDM needs both leading and trailing chips - as opposed to intel who mostly only wants N and N+1 - allowing Samsung some of that never ramp down goodness that TSMC enjoys even without factoring in Samsung Foundry.
Q1/21 estimates from an old semiwiki article posted by SJ:
View attachment 1625
Considering that scale is yield and that scale is cost, it is my opinion that continuing to keep pace with TSMC's scale on the leading edge will be critical to long term sustainability. Given the negative impact that I assume chiplets will have on scale I'm personally in the camp that leading edge IFS customers will be essential to maintaining the scale needed to thrive as capital intensity and R&D investment continue to increase. Additionally trailing edge chiplets and perhaps more importantly trailing IFS customers
should be a great boon to intel's finances.