Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/tsmc-180nm-130nm-and-110nm-nodes-release.17332/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021270
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

TSMC 180nm, 130nm and 110nm nodes Release

AmandaK

Administrator
Staff member
The Certus design team is constantly expanding our collection of high-performance Digital and Analog IO. In May their customers released three new chips in TSMC 180nm, 130nm and 110nm nodes. These IC’s included specialized Certus IO technologies. One such example was a 1.2V to 3.3V capable multi-function GPIO that’s is able to fully comply with SPI, I2C and I3C IO standards, all while exceeding 4kV HBM targets in a footprint smaller than the foundry and competing IO Libraries. Additional silicon proven designs in these releases included a complete Rad-Hard/High Temperature tolerant IO Library with GPIO’s, LVDS PHY’s (TIA-644/Spacewire complaint) and Open-Drain IO’s (Fail-Safe I2C/I3C complainant).
https://certus-semi.com/october-2013-october-2020-news/
Link to Press Release
 
Top