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TSMC 10nm Tools are ready!

Daniel Nenni

Admin
Staff member
The word on the street is that 10nm process design kits (PDKS)are correlating "as expected" with test silicon so we may in fact see 10nm first silicon in 2H 2016. I highly doubt it will be in time for the massive volumes of the Apple A10 but it will most certainly be ready for the A11.

It really is an exciting time in semiconductors and I am truly honored to be part of the fabless semiconductor ecosystem, absolutely. We are changing the world! Just wait for the medical applications to hit..... Quality of life will jump yet again and our children, grandchildren, etc... will hopefully live more comfortable lives.




TSMC Certifies Mentor Graphics
Tools for Early Design Start in TSMC’s 10nm FinFET Technology
WILSONVILLE, Ore., April 6, 2015—Mentor Graphics Corp. (NASDAQ: MENT) today announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre® physical verification and design for manufacturing (DFM) platform, and the Analog FastSPICE™ (AFS™) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models. New tool feature enhancement based on 10nm process requirements has been made in Olympus-SoC™ digital design platform with TSMC validation, and certification of full chip integration is actively on-going. In addition to 10nm, Mentor has also completed 16FF+ version 1.0 certification of the Calibre, Olympus-SoC and AFS platforms. These certifications provide designers with the earliest access to signoff technology optimized for TSMC’s most advanced process nodes, with improved performance and accuracy.


“The long-term partnership we have with Mentor Graphics enables us to work closely from the earliest phases of technology development so we can have production ready design kits and software available for our customers concurrently with the announcement of new process offerings,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Mentor’s design solutions have successfully met the accuracy and compatibility requirements for TSMC 10nm FinFET technology, so customers can initiate their designs with accurate verification solutions.”


The Analog FastSPICE Platform provides fast circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. For large circuits the AFS Platform also delivers high capacity and fast mixed-signal simulation. For embedded SRAM and other array-based circuits, AFS Mega delivers highly accurate simulation results.
As circuit reliability remains a focus, Mentor and TSMC have enhanced the Calibre PERC™ product offering in 10nm to ensure that design and IP development teams have robust verification solutions for identifying sources of electrical error. Additionally, the Calibre xACT™ extraction suite includes updated models to deliver more accurate results to fulfill tighter accuracy requirements of 10nm.


For TSMC’s 16FF+ 1.0 Calibre design kit release, the Calibre team has worked with TSMC to speed up DRC performance by 30% on average. In addition, TSMC and Mentor released new filling use models that will improve first-pass fill runs, making ECO changes easier and faster. The new fill methodology will also help ensure consistent cycle times during post fill verification.


“Because Mentor and TSMC work together from the earliest stages of design rule development for a new process node, we learn what the new design and verification challenges are right along with TSMC.” said Joseph Sawicki, vice president and general manager of the Design to Silicon division at Mentor Graphics. “This gives us the ability to have the most advanced capabilities in place for ecosystem early adopters, and to continue to optimize performance as the new process moves to full production status.”

About Mentor Graphics


Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.24 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics and Calibre are registered trademarks and PERC, xACT, Olympus-SoC, Analog FastSPICE and AFS are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)
For more information, please contact:
Gene Forte
Mentor Graphics
503.685.1193
gene_forte@mentor.com

 
Another EDA vendor with qualified tools at TSMC 10 nm is ATopTech for place & route. FYI - the CEO of ATopTech and several others used to work at Mentor Graphics.

ATopTech Collaborates with TSMC on 10nm Automatic Place and Route Design
Enablement and Tool Certification


Collaboration ensures that Aprisa and Apogee will be ready for joint
customers to start evaluations/ /designs for 10nm process node


SANTA CLARA, CA - April 6, 2015 -- ATopTech, the leader in next generation
physical design solutions, is collaborating with TSMC <http://www.tsmc.com>
to certify Aprisa(tm) and ApogeeTM, ATopTech's place and route solutions,
for TSMC 10nm process technology ATopTech <ATopTech Home> has
long collaborated with TSMC for advanced processes, starting with 28nm and
20nm and moving through 16FinFET (16FF) and 16FinFET+ (16FF+). The success
of this continuing collaboration has resulted in ATopTech being designated
as a "Partner of the Year" by TSMC in 2012, 2013 and 2014.


Aprisa <ATopTech Aprisa> (tm) and Apogee
<ATopTech Apogee> TM advanced physical implementation
solutions deliver optimum runtime, quality of results and yield.


"Our continuing collaboration with TSMC at 10nm ensures that Aprisa and
Apogee will be ready for joint customers to start evaluations and designs
for the 10nm process, giving them an advantage in automatic
place-and-route," said Jue-Hsien Chern, CEO of ATopTech. "As always, it is
our pleasure to work with TSMC to ensure the highest possible routability
for leading-edge technology nodes."


About Aprisa


Aprisa is a complete place-and-route (P&R) engine, including placement,
clock tree synthesis, optimization, global routing and detailed routing. The
core of the technology is its hierarchical database. Built upon the
hierarchical database are common "analysis engines," such as RC extraction,
DRC engine, and an advanced, extremely fast timing engine to solve the
complex timing issues associated with OCV, signal integrity (SI) and
multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art
multi-threading and distributed processing technology to further speed up
the process. Because of this advanced architecture, Aprisa is able to
deliver predictability and consistency throughout the flow, and hence faster
total turn-around time (TAT) and best quality of results (QoR) for physical
design projects.


About Apogee


Apogee is a full-featured, top-level physical implementation tool that
includes prototyping, floorplanning, and chip assembly. The unified
hierarchical database enables a much more streamlined hierarchical design
flow. Unique in-hierarchy-optimization (iHO) technology helps to close
top-level timing during chip assembly through simultaneous optimization at
top level and at blocks, reducing the turnaround time for top-level timing
closure from weeks to days.


About ATopTech


ATopTech, Inc. is the technology leader in IC physical design. ATopTech's
technology offers the fastest time to design closure focused on advanced
technology nodes. The use of state-of-the-art multi-threading and
distributed processing technologies speeds up the design process, resulting
in unsurpassed project completion times. For more information, see
www.atoptech.com


# # #


Aprisa and Apogee are trademarks and ATopTech is a registered trademark of
ATopTech, Inc. Any other trademarks or trade names mentioned are the
property of their respective owners.
 
TSMC showed ecosystem slides today and ATopTech was not finished with 10nm certification. Only Cadence, Synopsys, Mentor, and ANSYS.
 
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