Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/tsmc-1-4nm.16038/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020970
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

TSMC 1.4nm

Scotten Jones

Moderator
There are reports out of Asia that TSMC 3nm development team is switching to 1.4nm and speculation about what that means. The speculation suggests 1.4nm is next after 3nm or replaces 3nm or.....

Here is my take:

3nm is due to enter production shortly, therefore development is done.
2nm development is underway and due for risk starts 2024 and production 2025 per TSMC last conference call.

My guess is the recent 1.4nm talk is because TSMC 3nm development team is now freed up with 3nm going into production and they are being reassigned to work on 1.4nm as the follow on to 2nm. I would expect 1.4nm in the 2026/2027 time frame at the earliest. I do not expect TSMC to skip 2nm, they have struggled with 3nm already.
 

Xebec

Active member
I'm curious if these leaks are real or not. With Intel having "2.0" and "1.8" nodes on their official roadmap (20A and 18A), it's interesting the rumors are TSMC will go from "2" to "1.4". I know it's all marketing, but...
 

Scotten Jones

Moderator
I'm curious if these leaks are real or not. With Intel having "2.0" and "1.8" nodes on their official roadmap (20A and 18A), it's interesting the rumors are TSMC will go from "2" to "1.4". I know it's all marketing, but...
I expected TSMC to follow 2nm with something like 1.5nm so 1.4nm doesn’t surprise me. What will be really interesting is how it is made. 2nm is pretty much known to be horizontal nanosheets (HNS),1.4nm could be a second generation HNS or we could see a CFET.
 

Daniel Nenni

Admin
Staff member
From Gartner: $50k for wafers at 1.4nm. Mask sets likely > $100M. Does that jibe with your numbers Scott?

Gartner Wafer Costs.jpg
 

Scotten Jones

Moderator
From Gartner: $50k for wafers at 1.4nm. Mask sets likely > $100M. Does that jibe with your numbers Scott?

View attachment 750
I am laughing right now, this chart made my day. Divide the wafer price by 2 and you will be close, the mask set cost is off by even more. There is a limit to how much wafer prices can go up with each new node if you want to sell them, $50k is way outside of that range and way outside of the cost with a reasonable margin.
 

Paul2

Active member
I am laughing right now, this chart made my day. Divide the wafer price by 2 and you will be close, the mask set cost is off by even more. There is a limit to how much wafer prices can go up with each new node if you want to sell them, $50k is way outside of that range and way outside of the cost with a reasonable margin.

If these people think that only super duper high value, low volume, large dies will be fabbed on those nodes in the future, they may make such assumption.

Very likely Gartner got their digits from companies doing that kind of stuff. Apple, or Qual/Broad-comm would guard the deal price with TSMC better than anything.

I remember Gartner once said that component price of an iPhone was $500 by looking up retail cost of its components...
 

GS Wallacce

New member
Has anyone on this forum seen a nice summary of modern node (say 14nm or 7nm and smaller) mask costs and perhaps(?) a list of the modern devices made using those and smaller nodes - in terms of rough unit volumes which must be realized to justify costs and a reasonable ROI? Scotten Jones (above), whom I have seen speak at SEMI ISS in the past, seems to treat the Gartner data table with a good measure of incredulity - and - comic relief. I have spent last 22 years in compound semi and have no links or easy access to this type of Si-process based data.
 

Scotten Jones

Moderator
Has anyone on this forum seen a nice summary of modern node (say 14nm or 7nm and smaller) mask costs and perhaps(?) a list of the modern devices made using those and smaller nodes - in terms of rough unit volumes which must be realized to justify costs and a reasonable ROI? Scotten Jones (above), whom I have seen speak at SEMI ISS in the past, seems to treat the Gartner data table with a good measure of incredulity - and - comic relief. I have spent last 22 years in compound semi and have no links or easy access to this type of Si-process based data.
I have all of that.
 
Top