TSMC’s AI Chip Capacity Growth Ahead Of Schedule Says Morgan Stanley – Report

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Investment bank Morgan Stanley believes that the Taiwan Semiconductor Manufacturing Company (TSMC) will be able to expand its CoWoS chip packaging capacity a year ahead of schedule. TSMC was initially slated to grow its packaging capacity by 2026, but as per the bank, this has moved ahead by a year to 2025.

Packaging demand has grown in the wake of the AI wave and has been one of the key constraints in the industry, which has ordered hundreds of thousands of GPUs primarily from NVIDIA Corporation. Morgan Stanley's optimism is also reflected in its share price target for TSMC, which the bank has raised from NT$1,220 to NT$1,280.

According to a report in the Taiwanese media, Morgan Stanley analyst Zhan Jiahong estimates that TSMC's original plan to increase CoWoS packaging capacity to 80,000 wafers per month by 2026 is moving faster than expected. As a result, the firm can achieve this goal by 2025 instead, with the timeline benefiting favorably from TSMC's acquisition of a NT$17 billion factory in Taiwan in August.

The analyst is also optimistic about TSMC's current leading edge 3 nanometer chip manufacturing process. He believes 3nm capacity can grow from 90,000 wafers per month in 2024 to 120,000 wafers per month in 2025. As is the case with packaging, demand from the artificial intelligence industry is slated to aid the capacity bump.

For the latest AI chips, packaging and fabrication have to go hand in hand as the latter ensures performance superiority and power efficiency; the former is responsible for assembling the chips into a usable form for the end product.

The demand for TSMC's 3nm process technology is also expected to be boosted by Intel shifting some of its chip manufacturing needs to the company. While this assumption is reflected in the analyst's model, the bank is unable to confirm whether this will be the case in reality. Chip demand for the iPhone is expected to play a role in the capacity increase, particularly as Apple's 2025 iPhone should remain on the 3nm node and use the advanced N3P variant.

TSMC is also expected to grow the capacity of its latest manufacturing technology, the 2 nanometer node. Even though Apple's orders will not materialize next year, Morgan Stanley believes that 2nm production can scale from 10,000 wafers per month in 2024 to 50,000 wafers per month in 2025. This will further grow to 80,000 wafers per month in 2026 as the 2026 iPhone ramps up production. By 2026, the 3nm capacity is slated to touch 140,000 wafers per month, which will include 20,000 from TSMC's manufacturing facilities in the US.

The Morgan Stanley analyst also raised his 2025 capital expenditure estimate for 2025. He believes that it will grow by 8.5% in 2025, or from $35 billion this year to $38 billion in the next year. Geopolitical tensions coupled with soaring demand for AI have required TSMC to expand its manufacturing capacity and diversify its production base away from Taiwan. These plans have included opening new plants in the US and Japan, with media reports also stating that discussions are underway to set up chip manufacturing facilities in the water scarce region of the Middle East.

TSMC's AI Chip Capacity Growth Ahead Of Schedule Says Morgan Stanley - Report

Investment bank Morgan Stanley raises TSMC's share price target due to earlier than expected packaging capacity expansion and strong demand.

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[Daniel Nenni]

And TSMC will only package TSMC die....... Packaging really is a big competitive moat around TSMC.

 

[Paul2]

What is "AI chip capacity"?

 

[Daniel Nenni]

What is "AI chip capacity"?

Right now it is mainly GPU capacity (Nvidia) which includes CoWoS. Packaging is definitely the bottleneck right now but that will not be the case in the coming years. Building and staffing CoWoS capacity is much easier than building and staffing wafer fabs. TSMC Cowos packaging should more than double this year and next year and probably the year after. Problem solved in my opinion.

If you look at semiconductor growth there is unit growth and ASP growth. Right now ASP growth is outpacing unit growth so the need for extra capacity is not always what it seems.

 

[hist78]

And TSMC will only package TSMC die....... Packaging really is a big competitive moat around TSMC.

In theory, Intel's advanced packaging can combine "tiles" from different manufacturers. Has Intel ever achieved that in terms of major tiles? The packaging for Lunar Lake and Arrow Lake is done by Intel, but all the major tiles are made by TSMC. Beyond cost, performance, delivery schedule, and capacity considerations, could it also be that packaging major chiplet components from multiple vendors is currently too complicated for Intel or TSMC?

 

[hist78]

Right now it is mainly GPU capacity (Nvidia) which includes CoWoS. Packaging is definitely the bottleneck right now but that will not be the case in the coming years. Building and staffing CoWoS capacity is much easier than building and staffing wafer fabs. TSMC Cowos packaging should more than double this year and next year and probably the year after. Problem solved in my opinion.

If you look at semiconductor growth there is unit growth and ASP growth. Right now ASP growth is outpacing unit growth so the need for extra capacity is not always what it seems.

It's interesting how important TSMC's advanced packaging solutions, like CoWoS, have become for companies like TSMC, Nvidia, Apple, AMD, and many others, driving their products, revenue, and profit. It wasn’t like this when TSMC first introduced its advanced packaging solutions about 14-15 years ago. In fact, Nvidia was one of the companies that rejected the idea back in those early days.

TSMC's first win in advanced packaging came from Xilinx, which placed an order for just 50 wafers per month. Yes, a whopping 50 wafers per month!

TSMC's former CTO, Shang-Yi Chiang, recalled that he became the subject of laughter at TSMC for investing about $100 million and 400 engineers into the R&D for advanced packaging—only to secure an order of 50 wafers per month.

 

[Daniel Nenni]

It's interesting how important TSMC's advanced packaging solutions, like CoWoS, have become for companies like TSMC, Nvidia, Apple, AMD, and many others, driving their products, revenue, and profit. It wasn’t like this when TSMC first introduced its advanced packaging solutions about 14-15 years ago. In fact, Nvidia was one of the companies that rejected the idea back in those early days.

TSMC's first win in advanced packaging came from Xilinx, which placed an order for just 50 wafers per month. Yes, a whopping 50 wafers per month!

TSMC's former CTO, Shang-Yi Chiang, recalled that he became the subject of laughter at TSMC for investing about $100 million and 400 engineers into the R&D for advanced packaging—only to secure an order of 50 wafers per month.

"TSMC's former CTO, Shang-Yi Chiang, recalled that he became the subject of laughter at TSMC for investing about $100 million and 400 engineers into the R&D for advanced packaging—only to secure an order of 50 wafers per month."

I remember this,! I believe it was at 28nm. I was working with Xilinx at the time. We did a full chapter on Xilinx in our Fabless book. Xilinx had one of the best foundry teams in the industry. Once Xilinx partnered with TSMC (28nm) Altera took a beating with Xilinx beating them to silicon at every node including 28nm.

Shang-Yi was a true visionary! They should name a packaging facility after him. I believe he is at Foxconn now. ChaptGPT says he is:

Yes, Chiang Shang-yi is still with Foxconn. After joining Foxconn in late 2022 as a top semiconductor adviser, he has been involved in guiding the company’s semiconductor strategy. Chiang is helping Foxconn, primarily known for assembling Apple products, expand its semiconductor ambitions as part of its efforts to diversify into new technology areas.

 

[Daniel Nenni]

In theory, Intel's advanced packaging can combine "tiles" from different manufacturers. Has Intel ever achieved that in terms of major tiles? The packaging for Lunar Lake and Arrow Lake is done by Intel, but all the major tiles are made by TSMC. Beyond cost, performance, delivery schedule, and capacity considerations, could it also be that packaging major chiplet components from multiple vendors is currently too complicated for Intel or TSMC?

I thought Intel had already integrated Intel and TSMC chiplets? I do not think TSMC has a technical problem integrating chiplets from other fabs. It is a CoWos capacity issue, exclusive TSMC customers are first in line and it is a long line.

 

[Maximus]

I thought Intel had already integrated Intel and TSMC chiplets? I do not think TSMC has a technical problem integrating chiplets from other fabs. It is a CoWos capacity issue, exclusive TSMC customers are first in line and it is a long line.

The first Intel product to feature both Intel and TSMC chiplets was likely Ponte Vecchio, though it had a short lifespan and was discontinued after fulfilling orders for the National Lab. More recently, Meteor Lake has also integrated chiplets from both Intel and TSMC in its packaging.

 

[hist78]

I thought Intel had already integrated Intel and TSMC chiplets? I do not think TSMC has a technical problem integrating chiplets from other fabs. It is a CoWos capacity issue, exclusive TSMC customers are first in line and it is a long line.

The first Intel product to feature both Intel and TSMC chiplets was likely Ponte Vecchio, though it had a short lifespan and was discontinued after fulfilling orders for the National Lab. More recently, Meteor Lake has also integrated chiplets from both Intel and TSMC in its packaging.

It’s true that Intel has successfully packaged chips using both Intel-made and TSMC-made components. However, it’s important to note that even those components made by TSMC are still designed by Intel, which likely makes the packaging integration more feasible and manageable.

But my deeper question is: Can Intel’s packaging services handle chiplet components that are not designed by Intel and are instead manufactured by other foundries like GlobalFoundries, UMC, or Tower Semiconductor?

 

[Xebec]

It’s true that Intel has successfully packaged chips using both Intel-made and TSMC-made components. However, it’s important to note that even those components made by TSMC are still designed by Intel, which likely makes the packaging integration more feasible and manageable.

But my deeper question is: Can Intel’s packaging services handle chiplet components that are not designed by Intel and are instead manufactured by other foundries like GlobalFoundries, UMC, or Tower Semiconductor?

Intel did a few limited volume products of this in the past — they had a few mobile devices that they packaged with parts from 3 different fabs/foundries.

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The CPU was fabbed on Intel 14nm, and the Vega GPU was (IIRC) GloFo 14nm. These were coupled with HBM2, presumably made by someone else (Samsung?).