Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/trends-in-asic-verification.833/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021270
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Trends in ASIC verification

DVCON 2011 held at San Jose between FEB 28 to MAR 3 was quite a success. While UVM dominated the conference, the keynote by Walden Rhines was quite very interesting. The presentation, “</SPAN>From Volume to Velocity</SPAN></SPAN>” touched upon the what’s going on in verification for past few years and challenges for future. Some of the interesting facts highlighted in the presentation were an outcome of one of the largest functional verification studies</SPAN> carried out by Wilson Research Group in 2010, commissioned by Mentor Graphics. Harry Foster has been writing a series of blogs</SPAN> summarizing this study.</SPAN></SPAN>

Read on for trends in ASIC design & verification... Verification Trends
 
Last edited:
Top