Scotten Jones
Moderator
I agree with Ian, backside power will be introduced at 2nm, it will not be used for larger nodes.
The viability of CFET alternatives?
- Thread starter nghanayem
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Scotten Jones
Moderator
Why do you think VFET is a pre-requisite for monolithic 3D, monolithic CFETs with HNS have already been demonstrated and I personally know of work being done or more than 2 layers.
Scotten Jones
Moderator
The benefits don't justify the cost and complexity.
If we define "DUV" processes as 8nm and above, Backside power delivery (BSPD) solves two problems at the leading edge that don't exist for "DUV":
1) BSPD can reduce the width of the cell boundary enabling 5 track or shorter cell height, but all the 8nm and larger nodes are >7.5 tracks and don't need it. The more tracks the smaller the gain from reducing the cell boundary and to really get to smaller track heights you have to go from 3 to 2 fins and that is a whole new process design to maintain performance.
2) For leading edge processes the metal stacks have a lot of layers with small lines and small vias. Bringing power in through the front of the wafer means the power has to travel down to the surface through long via chains. For TSMC 3nm with 15 metals, the resistance is ~550 ohms. For 8nm and above there are less metal layers, bigger metal lines and bigger vias and therefore less resistance.
Any foundry implementing BSPD would have to recharacterize their process and build new PDKs, then designs would have to be done with the new PDK. The costs of new designs, new masks, yield learning all for something with little benefit just doesn't make sense to me.
A fab implementing this would also need new equipment, most fabs don't have bonders and grinders or the right etching and polishing equipment, the requirements to thin the wafer to the levels required are very challenging. The fabs may not have space to add the required equipment.
I would also not underestimate how hard BSPD is going to be, the wafer will need to be very thin to get the resistance benefit. Both Samsung and TSMC are introducing 2nm without BSPD and then doing a second generation with BSPD.
Scotten Jones
Moderator
With respect to HNS, they are a natural evolution from FinFETs with 85-90% of the process steps in common. HNS have better electrostatic control than FinFETs and gets you about 3nm in Lg resulting in smaller CPP. They also provide better Weff per unit of horizontal area.
Once you are into HNS then you can shrink cell height by reducing n to p spacing with a dielectric wall (forksheet) or eliminate horizontal n to p spacing by going to a CFET.
Longer term you replace the nanosheets with 2D material and you get about 10nm of Lg reduction, better capacitance, and better performance all around.
That is really the advantage of HNS, evolution from FinFET and over a decade of scaling opportunity.
Once you are into HNS then you can shrink cell height by reducing n to p spacing with a dielectric wall (forksheet) or eliminate horizontal n to p spacing by going to a CFET.
Longer term you replace the nanosheets with 2D material and you get about 10nm of Lg reduction, better capacitance, and better performance all around.
That is really the advantage of HNS, evolution from FinFET and over a decade of scaling opportunity.
Since you have used 8nm in your EUV example, can you tell me the your estimated resistance VIA resistance from the shared met1 between the stdcell rows going down to the bottom substrated compared to the via resistances that would go up to thick layers above? That would be more telling. How large would you expect these TSV vias to be? Are they rectangular (I assume they can be wide?).
I will agree to disagree with you on the PDK side. I will leave it at that.
As far as the fabrication difficulty, that is really my question. I assume that is the area that you have expertise in?
I will agree to disagree with you on the PDK side. I will leave it at that.
As far as the fabrication difficulty, that is really my question. I assume that is the area that you have expertise in?
It seems like TSMC and intel are much more interested with all in one go CFET than FS or bonded CFET. Wanting to do CFET all in one go makes sense, but why does FS not seem to get any love? It feels like an easy scaling booster. Is it possible it is so easy that they don’t bother talking about it? Or is CFET coming sooner than we expected?
Scotten Jones
Moderator
Forksheet is basically making a HNS into a FinFET turned on it's side and you lose some electrostatic control
Scotten Jones
Moderator
I don't have specific numbers for 8nm, I just picked that because it is the last generation before EUV at the foundries. The key point to me is resistance was always an issue but a manageable one and it wasn't until recently that it became such a problem that people started looking at solutions like BSPD.
I am not a design guy but I know several including Ian who I have tremendous respect for from years of interactions.
Yes, I have designed, built and run wafer fabs and sustained and developed processes. BSPD is a very challenging process.
I was aware of this. But my understanding was FS was still better than finFET in this regard, and it is not as if CFET won’t have performance implications (probably even worse). I figured if we were willing to deal with the capcitance and heat issues for a much harder architecture, then FS would be an easy thing to add while the kinks for CFET get worked out.
Mooredaddy
Well-known member
What is the long term outlook for the likes of GF and UMC anyways. Not that I’m implying their current business is going away or they are in existential danger or anything but their upward movement in the market seems to me to be hard capped. Sure they will build out legacy capacity but they really do seem destined to being ground down into a less and less differentiated product over time. I wonder what the breakdown of their output will be in 5-10 years time.
The goal is a System In a Package, not just a monolithic. A good goal is to minimize the PC board and FPGA with an ASIC. Not all chips land in the data center, cell phone tower, and the cell phone. IMO, there is too much focus/press on this insane and prohibitively expensive 13.5nm wavelength technology. What's next for ASML, the transporter beam?
If GF and Skywater are able to perfect their technologies (14nm, TSVs, multichip packaging, MEMs, exotic memory), they should do quite well. I think their strategy is excellent. Execution... we will see. The Miata outsold the Lotus
UMC is a whole different issue
If GF and Skywater are able to perfect their technologies (14nm, TSVs, multichip packaging, MEMs, exotic memory), they should do quite well. I think their strategy is excellent. Execution... we will see. The Miata outsold the Lotus
UMC is a whole different issue
That's what's called sequential 3D. A new EPI or oxide layer is desposited, and then they make a N or P MOS part of a CMOS on top of it.
VTFET allows to etch single vertical channel which will then be used by multiple devices built directly on top of each other. An entire 6T SRAM cell can hypothetically made by stacking 2x3 or 6x1 devices on top of each other.
To add on to this a monolithic CFET can also get two layers with one etch. However it is hard to imagine how you can scale fin height enough to get 4 and above layers.
Never forget physics.
In CMOS you want a well behaved switch and this impose a lot of constraints for electrostatics. When you look at nanowires/sheets, regardless of their orientation in space, you have some critical dimensions you cannot ignore so there are limits (lower and upper) for the thickness of such layers. If you stay on the horizontal plane for your channels, you choose the best thickness of the wire/sheet for electrostatic control and adapt the x/y dimensions for other optimisations. And if you need more current you just superimpose more wires/sheets without loss of density. Source and drain are coplanar and you can access them and have them fully symmetrical, same for the gates. If you go vertical, as before the electrostatic impose the diameter of the wire but now it also fixes your W as it is the circumference of the wire. If you need more current you need wore wires and you lose surface density. You are re-introducing the link between W and the area taken by the device as it was between finfet. You get away with that for VNAND as you can do with lousy transistors, the design is a highly regular structure and the pitches are relatively large, but logic is another beast and you need more than just SRAM even if it is a dominant part of the design. In the examples above you have that all the transistor in the same column have the same W, that is a big restriction for design, just consider matching p and n currents.
Moreover, vertical channels are not symmetric as the extension you will need for S/D contacts on top or bottom will have different geometries as you can see from some of the previous figures. And schemes like those sometimes looks more as a show-off of mastering Coventor than a real process flow with an associated reticle set.
Do not forget routing: anywhere one of those local interconnects needs to get to a metal line for distribution you cannot put transistors on top so you have an extra density loss.
3D is certainly the way forward but is not easy and not all challenges are solved, one of those is place and route in real 3D and not 2.5D. Another is the capability of having good epi growth on very small areas and then propagating it vertically. Some of the monolithic 3D demonstrations have been either on very large structures or using bonding of crystalline layers on top of insulators. And keeping the strain that gives you the carrier mobility in some of those structures will also be challenging.
They should merge IEDM and ISSCC and have more plenary sessions so that device/process/circuit people talks more to each other ....
In CMOS you want a well behaved switch and this impose a lot of constraints for electrostatics. When you look at nanowires/sheets, regardless of their orientation in space, you have some critical dimensions you cannot ignore so there are limits (lower and upper) for the thickness of such layers. If you stay on the horizontal plane for your channels, you choose the best thickness of the wire/sheet for electrostatic control and adapt the x/y dimensions for other optimisations. And if you need more current you just superimpose more wires/sheets without loss of density. Source and drain are coplanar and you can access them and have them fully symmetrical, same for the gates. If you go vertical, as before the electrostatic impose the diameter of the wire but now it also fixes your W as it is the circumference of the wire. If you need more current you need wore wires and you lose surface density. You are re-introducing the link between W and the area taken by the device as it was between finfet. You get away with that for VNAND as you can do with lousy transistors, the design is a highly regular structure and the pitches are relatively large, but logic is another beast and you need more than just SRAM even if it is a dominant part of the design. In the examples above you have that all the transistor in the same column have the same W, that is a big restriction for design, just consider matching p and n currents.
Moreover, vertical channels are not symmetric as the extension you will need for S/D contacts on top or bottom will have different geometries as you can see from some of the previous figures. And schemes like those sometimes looks more as a show-off of mastering Coventor than a real process flow with an associated reticle set.
Do not forget routing: anywhere one of those local interconnects needs to get to a metal line for distribution you cannot put transistors on top so you have an extra density loss.
3D is certainly the way forward but is not easy and not all challenges are solved, one of those is place and route in real 3D and not 2.5D. Another is the capability of having good epi growth on very small areas and then propagating it vertically. Some of the monolithic 3D demonstrations have been either on very large structures or using bonding of crystalline layers on top of insulators. And keeping the strain that gives you the carrier mobility in some of those structures will also be challenging.
They should merge IEDM and ISSCC and have more plenary sessions so that device/process/circuit people talks more to each other ....
Even as an SRAM die only process, it will be awesome, and grant an incredible economic advantage. Imagine the prospect of 1-2GB L3 on budget SoCs, and CPUs. I think you would be able to even forego putting in DRAM for embedded products in this case.
Scotten Jones
Moderator
Imec developed an incredibly dense vertical FET (VFET) SRAM with a relatively simple process flow years ago and my understanding is no one is interested in it. As far as I can tell none of the leading edge logic companies are working on vertical FETs. When I first saw it I thought it would be a great and inexpensive solution for SRAM only die, but again no one appears to have picked it up.
For logic, everyone is going to horizontal nano sheets (HNS), then CFETs and beyond that likely 2D. HNS has roughly 90% of the process in common with FinFETs and once you are making HNS you have Forksheets, CFET and 2D as scaling options. In my opinion HNS is the first step in at least ten more years of scaling. I don’t see VFET having that kind of long term scaling path plus for logic I have heard it is hard to interconnect.
Scotten, one lesson I learned with monolithic 3D is that a good technological solution doesn't get picked up if it doesn't cover all the spectrum of products. If can only do SRAM and not general purpose logic is a no go. One of the option we looked into with monolithic 3D was to put all the SRAM on the top layer and all the logic in the bottom so that one can separatly optimise and reduce overall chip area. Worked technologically and on initial benchmarks, but on real life type design the gain was not enough to move people off the standard roadmap. Hopefully all that work will be useful for the development of CFET as it is technologically quite similar.
VFETs have the intrinsic issue of the diameter fixing the W of the transistor and the thickness of the gate layer fixing the L of the transistor. Tell designers that increasing W reduce density and that all L need to be the same for the entire chip and they will start screaming. Dealing with a layer that need different thicknesses on the same plane is quite challenging and costly. It was the initial design benchmarks that killed the project at my place before it started.
VFETs have the intrinsic issue of the diameter fixing the W of the transistor and the thickness of the gate layer fixing the L of the transistor. Tell designers that increasing W reduce density and that all L need to be the same for the entire chip and they will start screaming. Dealing with a layer that need different thicknesses on the same plane is quite challenging and costly. It was the initial design benchmarks that killed the project at my place before it started.
jms_embedded
Active member
just for the context:
community.cadence.com
IEDM: Backside Power Delivery
<a href="https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes"></a>One part of the short course that I attended at IEDM in December was about backside power delivery networks. It was presented by Gaspard Hiblot of imec and titled Process Architectures Changes to Improve Power...
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