The viability of CFET alternatives?

[SPQR54]

The flow has some process steps similar/common with that proposed by CEA-Leti for the monolithic 3D (that by the way was partly generated by the idea of putting the SRAM on top of the logic as it was going to stagnate in density at some point). And one of the objections by foundries was that in the flow you mix font end and back-end processing. This not only creates issues for the contamination but also mess up the flow of wafers across the fab and the utilisation rate of the tools in currently designed fabs, it not only just a matter of adding a few tools. That is one of the main reason that this type of processes is going to appear only on completely new nodes in fabs thought specifically to address those issues and provided that the extra costs and the cycle times are still within market demands.
I share IanD opinion: in 30 years I have never seen a retrofit of new ideas in older technologies unless from a new player that had to do an initial qualification process anyway. I am from process but I have to say that design environment development and qualification of IP are becoming dominant economic factor in the introduction of new technology.

 

[cliff]

They don't save the testbenches with the designs?

 

[Tanj]

Per an older paper from Nikon, I think they said DUV double patterning was 2.5-3X more expensive than DUV single.

Really? That surprises me. The mental model for double is to expose mask 1 for the 25 wafers in a FOUP, swap to mask 2, expose those same 25, then send them on for the photomask to be stabilized and developed. I am told the mask swap is automated at 193 and takes just a few seconds, with multiple masks loaded in the machines ready for versatile fab scheduling. The wafers need to be exposed for both masks within a short time for best resist quality, keeping them in the machine should reduce contamination risks and be the best case process time. Since CMP, prep, development, and etching are not doubled, the multiplier should be much less than 2.

What am I overlooking? were they just talking about multiplier for mask cost?

 

[nghanayem]

Really? That surprises me. The mental model for double is to expose mask 1 for the 25 wafers in a FOUP, swap to mask 2, expose those same 25, then send them on for the photomask to be stabilized and developed. I am told the mask swap is automated at 193 and takes just a few seconds, with multiple masks loaded in the machines ready for versatile fab scheduling. The wafers need to be exposed for both masks within a short time for best resist quality, keeping them in the machine should reduce contamination risks and be the best case process time. Since CMP, prep, development, and etching are not doubled, the multiplier should be much less than 2.

What am I overlooking? were they just talking about multiplier for mask cost?

It’s not just double exposure and mask swap. There are multiple multi patterning schemes. LELE is the most common and required double the ashing/clean and double the etch. SADP also requires you to double up on equipment. There is also LHLE. In LHLE you must harden the resist prior to the second litho step (this requires leaving the litho tool). Double patterning also requires more metrology tools and stricter process control. There is also the uptick in defect density you have to worry about. These issues compund even harder for tripple and quad patterning. Also note that any time you need to cycle wafers through a tool or across the fab massively contributes to days per mask layer (process is fast load locks/efems are slow).

 

[benb]

Backside power delivery: Wouldn’t it be nice to have some test results, something to support the statement “it’s like 2 nodes better”. It’s vaporware.

Having one of those thick wafers blow up in a critical loadlock, spreading metals throughout the front end, is existentially bad, and is why there have never been metals in the front end in 50 years of semiconductor fabs. So it would be nice to know how that little triffle gets solved.

Other that my trust issues with vaporware and 50 years of fab practice, sounds great.

 

[nghanayem]

Never mind that it is probably going into high volume in a little over a year at intel and guaranteed high volume at TSMC in a couple of years. If you can't be bothered to look at a flowchart and see the obvious fact that this is not that big of a process flow change (retaliative to GAA or finFET) with new tooling only required for the new process modules, then all I can say is wait a couple years when the big three blow your socks off as they start churning out ARM and x86 SOCs using BSPDNs by the hundreds of millions. To claim BSPD is vaporware would be like claiming HNS are vaporware; they are coming immenently and the challenges while hard are far from unsolvable.

On performance nobody reasonable has ever claimed that it is 2 nodes worth of PPW. N2 is adding it latter, so it is probably a smaller deal than HNS (in both difficulty and performance uplift). 20A is a 15% uplift over i3. If the expectation was that this technology would provide 30-40% PPW, people would have rushed to it sooner no matter the difficulties. 30-40% is a planar to finFET level PPW improvement! Of course nobody expected that, so it is only being introduced now when HNS are being introduced and as we reach the limits of EUV SALELE.

Also note in the current literature the BPRs/nTSVs are tungsten. Unlike Cu, W doesn't have diffusion issues. W is already used in the FEOL so BSPD would not introduce any metals that weren't already in the FEOL. The backside is not yet being all the way thinned down for direct contact (or having interconnects in the FEOL like with CFET), so the risk of BS BEOL Cu diffusing into the device layer is as unlikely as the same thing happening in the FS BEOL. It can only happen if you accidentally punch through to the devices

 

[Tanj]

It’s not just double exposure and mask swap. There are multiple multi patterning schemes. LELE is the most common and required double the ashing/clean and double the etch. SADP also requires you to double up on equipment. There is also LHLE. In LHLE you must harden the resist prior to the second litho step (this requires leaving the litho tool). Double patterning also requires more metrology tools and stricter process control. There is also the uptick in defect density you have to worry about. These issues compund even harder for tripple and quad patterning. Also note that any time you need to cycle wafers through a tool or across the fab massively contributes to days per mask layer (process is fast load locks/efems are slow).

Sure, but LELE etc are double/multiple patterning not multiple exposure in the way we were discussing, which was about masks. Yes, you can double mask the stencil used to start LELE in order to improve the control of the line edges, and there are even some double patterning done around non-linear features, but in general double exposure and double patterning are separate processes. It is legitimate to keep track of the costs on each separately - including balancing how to consider them as alternatives in some cases.

 

[Tanj]

I never said it was easy. And your right bonding is the hardest step. Besides that there is no reason that existing tools wouldn’t work. I wouldn’t be surprised if wafer handling robots had to be retaught (but that isn’t a big deal). Also you are mistaken, there are in fact metals on the front side. Outside of routing the BPRs up to M0, M1, or the devices themselves the FS BEOL is unchanged. BSPD is a scheme to avoid reducing metal pitches and increase performance. It is not for replacing the FS metal interconnects.

The bonding step is routine for BSI CMOS sensors, the first commercial devices to do sequential stacking in volume. Not easy, but not an unknown either. Sony builds its latest sensors with the transistors fabricated last, on the backside, which is an interesting reversal of the flow IMEC show.

Useful to read the original IMEC report: https://www.imec-int.com/en/articles/how-power-chips-backside. IMEC reports are usually coming out well after the sponsoring partners have moved the technology to their own teams to get ready for production and are fairly confident it is going to be real.

I wonder how having the devices buried a little deeper will affect heat dissipation which for CFET is expected to be denser heat sources. There is no mention of thinning the donor wafer after, or what materials go into the donor wafer. No doubt a lot of research on that.

 

[nghanayem]

Sure, but LELE etc are double/multiple patterning not multiple exposure in the way we were discussing, which was about masks. Yes, you can double mask the stencil used to start LELE in order to improve the control of the line edges, and there are even some double patterning done around non-linear features, but in general double exposure and double patterning are separate processes. It is legitimate to keep track of the costs on each separately - including balancing how to consider them as alternatives in some cases.

The Nikon paper in question was comparing multiple different double patterning schemes, and the discussion in question was a small tangent into multi-patterning vs EUV. The reason for that being that Cliff thought that the large number of DUV tools being made might mean that foundries were going to start adding backside metals to mature nodes.

 

[nghanayem]

I wonder how having the devices buried a little deeper will affect heat dissipation which for CFET is expected to be denser heat sources. There is no mention of thinning the donor wafer after, or what materials go into the donor wafer. No doubt a lot of research on that.

I could be wrong, but I don't think there are plans to thin the donor wafer. The donor wafer gives you something to hold the wafer by/provides structural integrity. As for heat dissipation BSPD should help and hurt (less resistance but transistors have heat above and below). CFET is a whole other can of very complicated worms. My guess is there will be an unavoidable drop in clocks/increase in dark silicon, but for the potential density upside I see it as worth it. My opinion for most applications who cares if clocks go down 30% if you can get like a 1.8x effective transistor count bump.

 

[Paul2]

Another wrench to throw in: the nano part in the HNS is trivial - layer thickness is controlled by deposition. In VTFET, making ultrathin, repeating high aspect features will be much more tricky.

VTFET may be naturally denser, but the gate performance will also be so-so.

VTFET however is a pre-requisite for monolithic 3D. And if you get mono 3D running, mono 3D changes everything.

 

[nghanayem]

Another wrench to throw in: the nano part in the HNS is trivial - layer thickness is controlled by deposition. In VTFET, making ultrathin, repeating high aspect features will be much more tricky.

VTFET may be naturally denser, but the gate performance will also be so-so.

VTFET however is a pre-requisite for monolithic 3D. And if you get mono 3D running, mono 3D changes everything.

Your logic is sound but IMEC, TSMC, and intel seem to disagree. If they peruse CFET as their way to crack monolithic 3D, then I would have to assume the IBM alliance will be forced to go that way as well.

 

[Paul2]

Your logic is sound but IMEC, TSMC, and intel seem to disagree. If they peruse CFET as their way to crack monolithic 3D, then I would have to assume the IBM alliance will be forced to go that way as well.

Mono-3D with existing devices, or HNS, will be just layering devices, and metal on new smooth epi layers, and connect layers with vias. Thus you will get close to linear scaling of process steps. With vertical devices, people will supposedly make long channel rods in one go first, and then build up things around them, and then you pour metal last. That's inherently better than O\(n\) scaling

 

[Paul2]

Another wrench to throw in: the nano part in the HNS is trivial - layer thickness is controlled by deposition. In VTFET, making ultrathin, repeating high aspect features will be much more tricky.

VTFET may be naturally denser, but the gate performance will also be so-so.

VTFET however is a pre-requisite for monolithic 3D. And if you get mono 3D running, mono 3D changes everything.

Saying that individual VTFET pillar electrostatics may be so so, you still get a process with SRAM density being many times better than FinFET can possibly be. And in case of complimentary VTFET, it's even bigger.

imec magazine September 2017 - The vertical nanowire FET: enabler of highly dense SRAMs

Gate-all-around nanowire field effect transistors (FETs) in a vertical configuration bring many opportunities, such as the 'super-scaling' of memory cells.

www.imec-int.com

 

[Paul2]

Now, imagine this thing being done with BPRs

 

[nghanayem]

View attachment 1003

Now, imagine this thing being done with BPRs

BPRs are a waste for this (only benefits the bottom transistors). Stack like NAND.

But people far more knowledgeable/experienced than me say that due to the random nature of logic designs this is non trivial due to the metal pitches required and high parasitic capacitance you would have to deal with. To me it seems like CFET with BPR is being chosen as a lower risk/challenge item even if the potential rewards are far less.

Source paper: (it is another excellent v-nanowire paper that integrated with some industry standard tools)

SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs

For sub-5nm technology nodes, gate-all-around (GAA) FETs are positioned to replace FinFETs to enable the continued miniaturization of ICs in the future. In this paper, we introduce SkyBridge-3D-CMOS 2.0, a 3D-IC technology featuring integration of stacked vertical GAAFETs and 3D interconnects...

ieeexplore.ieee.org

 

[Tanj]

But people far more knowledgeable/experienced than me say that due to the random nature of logic designs this is non trivial due to the metal pitches required and high parasitic capacitance you would have to deal with. To me it seems like CFET with BPR is being chosen as a lower risk/challenge item even if the potential rewards are far less.

If the vertical layers are costly - lots of process steps, added yield risk, why bother? If they have added capacitance which negates any perf advantage that proximity might bring, why bother?

A nice thing about ribbons/GAA is that the preparation - layers of perfectly controlled alternating Si/SiGe - is an epitaxial process of a kind well understood. No extra lithography, in principle it is about the same as FinFET. Yeah sure there are some tricky new things related to etch and fill, but you can squint at them and say "just chemistry, cheap once mastered". So it passes that first test, the areal density comes at acceptable cost. The perf may be meh? I don't know where that stands, but at least the first part is promising.

Skybridge looks like a bunch of extra process steps.

 

[nghanayem]

If the vertical layers are costly - lots of process steps, added yield risk, why bother? If they have added capacitance which negates any perf advantage that proximity might bring, why bother?

A nice thing about ribbons/GAA is that the preparation - layers of perfectly controlled alternating Si/SiGe - is an epitaxial process of a kind well understood. No extra lithography, in principle it is about the same as FinFET. Yeah sure there are some tricky new things related to etch and fill, but you can squint at them and say "just chemistry, cheap once mastered". So it passes that first test, the areal density comes at acceptable cost. The perf may be meh? I don't know where that stands, but at least the first part is promising.

Skybridge looks like a bunch of extra process steps.

The process flow is similar to 3D nand. So lots of deposition and you need very anisotropic etches. Litho steps shouldn’t be that bad. One litho process to make your rods, and one for each metal layer. Just like with tall fins my biggest concern with skybridge process flow would be your tall thin structures collapsing after you release them so you can build up your metal layers.

As for HNS you are correct very similar to finFETs. IMEC and many other researchers have published the devil is in the PMOS and HNS uniformity. I feel that just like HKMG last, once it is solved it is solved.

Speaking of I wonder if Samsung is using shorter fins or taller HNSs for 3GAE? They are only doing 3 sheets so I wonder where the extra space went and what benefits they are getting from this (as they will take a performance hit from not having four sheets).

 

[jms_embedded]

Those diagrams look like cat trees / towers, something for your pet to play on.... =)

 

[Tanj]

Those diagrams look like cat trees / towers, something for your pet to play on.... =)

I have some vertical-channel gain-cell designs which look a bit like those. But they only use 2T per bit, so rather denser.

At liquid N2 temperature like session 23.5 at IEDM 2022, a gain cell is effectively the same as an SRAM.