The viability of CFET alternatives?

[cliff]

Thank you Ian for your feedback. You brought up many good points that I found valuable.

For the others...

Imec demonstrates critical building blocks for a backside power delivery network | imec

In several papers presented at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec reports progress in developing enabling technologies for a backside power delivery network. First, the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices was...

www.imec-int.com

For the first time, imec has evaluated the impact of backside wafer thinning and n-TSV fabrication on the characteristics of scaled Si-channel FinFET test devices (gate length ≥20nm), built in the wafer’s frontside. The backside connectivity was realized through tungsten-filled n-TSVs that land on metal-1 pads in the wafer’s frontside. Naoto Horiguchi, director CMOS device technology at imec: “The most important conclusion of this work is that wafer thinning and n-TSV processing in the backside did not show any negative impact on the performance of the FinFETs, except for a slight degradation of the pMOS drive current. For nMOS, an even higher mobility and drivability (up to 15%) were found after backside processing, and no bias temperature instability (BTI) degradation was observed. In this work, wafers were thinned down to final Si thicknesses ranging between 20 and 370nm.” More details are included in the 2021 VLSI paper by A. Veloso et al. [VLSI-1]

=============================================

Imec must have done this expensive exercise for a reason, and their results appear to be encouraging. In 2025, the ASML CEO predicts 660 DUV machines vs 90 EUV machines will be produced. DUV double patterned processes seem to be more practical for ASICs.

As somebody who 1) Creates stdcells, P&R tools, analyzes EM and voltage drop on supplies, etc, and 2) helps customers with ASICs on DUV processes, I believe the benefits of the backside supply connections through the bottom of the substrate is huge.

Are there any other predictions out there by process people of the viability of GF, TSMC-Japan, and Intel doing this on their 12nm + processes?

 

[nghanayem]

Thank you Ian for your feedback. You brought up many good points that I found valuable.

For the others...

Imec demonstrates critical building blocks for a backside power delivery network | imec

In several papers presented at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec reports progress in developing enabling technologies for a backside power delivery network. First, the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices was...

www.imec-int.com

For the first time, imec has evaluated the impact of backside wafer thinning and n-TSV fabrication on the characteristics of scaled Si-channel FinFET test devices (gate length ≥20nm), built in the wafer’s frontside. The backside connectivity was realized through tungsten-filled n-TSVs that land on metal-1 pads in the wafer’s frontside. Naoto Horiguchi, director CMOS device technology at imec: “The most important conclusion of this work is that wafer thinning and n-TSV processing in the backside did not show any negative impact on the performance of the FinFETs, except for a slight degradation of the pMOS drive current. For nMOS, an even higher mobility and drivability (up to 15%) were found after backside processing, and no bias temperature instability (BTI) degradation was observed. In this work, wafers were thinned down to final Si thicknesses ranging between 20 and 370nm.” More details are included in the 2021 VLSI paper by A. Veloso et al. [VLSI-1]

=============================================

Imec must have done this expensive exercise for a reason, and their results appear to be encouraging. In 2025, the ASML CEO predicts 660 DUV machines vs 90 EUV machines will be produced. DUV double patterned processes seem to be more practical for ASICs.

As somebody who 1) Creates stdcells, P&R tools, analyzes EM and voltage drop on supplies, etc, and 2) helps customers with ASICs on DUV processes, I believe the benefits of the backside supply connections through the bottom of the substrate is huge.

Are there any other predictions out there by process people of the viability of GF, TSMC-Japan, and Intel doing this on their 12nm + processes?

The reason such large transistors were chosen is that it is A, easier to work with/debug (they do similar things with HNS and the like), and B IMEC isn't making a sellable product. A cool paper nonetheless and at 2nm and below BSPDN will be big performance and density enhancers.

 

[IanD]

Some technical details about BPD and some of the process challenges of getting it to work:

Challenges In Backside Power Delivery

BPD boosts performance, but requires wafer bonding, substrate thinning, and possibly new interconnect metals.

semiengineering.com

Some clues below as to why BPD is only being introduced at 2nm -- basically, lots of process and materials and flow changes are needed -- including quite a bit of detail about what IMEC are doing and why:

"Intel, Samsung and TSMC all have announced plans to implement BPD in some form at around the 2nm node."
"Nonetheless, a backside power network introduces substantial wafer processing challenges — especially since the change can occur at the same node as the device maker’s switch from finFETs to nanosheet transistors."
"Because BPD approaches are so new, the industry is weighing the pros and cons to different architectures."
“That is one reason why copper will never be used for this. It has to go through all the front-end processing, so it has to be compatible — something like tungsten or molybdenum, or maybe ruthenium.”
"Building these into the manufacturing flow is a challenge by itself."
"But several process and materials changes must be realized to make BPD a reality in production fabs. “For better area usage and performance enhancement, backside power delivery (BPD) network is an attractive option. For its enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies,”

Also see here:

TSMC: N2 To Start With Just GAAFETs, Add Backside Power Delivery Later

www.anandtech.com

Backside power delivery | imec

Future chips may well break the tradition of delivering power through the chip’s frontside: a backside power delivery network (BSPDN) has clear performance advantages.

www.imec-int.com

 

[Paul2]

I would expect TSMC to keep their foot on the gas pedal. The US will continue to use the printing press, lie about the real inflation rate, and pay whatever TSMC demands in the future. Satellites, drones, and missiles need sophisticated chips, and we are at war. Necessity is the mother of invention.

I highly doubt this will matter. In the case we will go to war against China, the lack of artillery shells will be a much deadlier threat than lack of chips, which can be stocked in great amounts. I.E. total physical chips volume of F35 programme is still less than one 300m wafer.

The dreaded saying is that US stocks of ammo would've held only for "8 to 16 weeks" of war with Russia. It was our great luck that Russia didn't turn into West in February, and instead went to attack the biggest army in Europe after itself.

The lack of shells is a screw up eclipsing the lack of microchips hundredfold, and this is what strategic planners and RAND consultants with 7 digit salaries didn't see. I bet we have way more such skeletons in the closet to uncover. US war needs can be undermined by things far more trivial than microchips, like our total dependence on foreign high performance bearings suppliers (no tanks, and jets if we lose it,) explosives (we have to import TNT to cover out shortage from as far as Australia,) steel (we are a literal nothing in front of countries with gigatons of steel production)

 

[nghanayem]

I highly doubt this will matter. In the case we will go to war against China, the lack of artillery shells will be a much deadlier threat than lack of chips, which can be stocked in great amounts. I.E. total physical chips volume of F35 programme is still less than one 300m wafer.

The dreaded saying is that US stocks of ammo would've held only for "8 to 16 weeks" of war with Russia. It was our great luck that Russia didn't turn into West in February, and instead went to attack the biggest army in Europe after itself.

The lack of shells is a screw up eclipsing the lack of microchips hundredfold, and this is what strategic planners and RAND consultants with 7 digit salaries didn't see. I bet we have way more such skeletons in the closet to uncover. US war needs can be undermined by things far more trivial than microchips, like our total dependence on foreign high performance bearings suppliers (no tanks, and jets if we lose it)

By war I think he meant a cultural/economic war.

 

[cliff]

Correct. The war is ultimately BRICS (really China) vs the US Dollar. The battles are control of technology, the seas (shipping), and energy.

 

[Paul2]

Correct. The war is ultimately BRICS (really China) vs the US Dollar. The battles are control of technology, the seas (shipping), and energy.

US has own oil, gas, and pretty much everything, and for a lot of things we can hurt them more with embargoes than with boycotts.

That's kind of nonsense.

 

[IanD]

US has own oil, gas, and pretty much everything, and for a lot of things we can hurt them more with embargoes than with boycotts.

That's kind of nonsense.

And that's a US-centric view. The world is bigger than the USA... ;-)

 

[cliff]

Like it or not, I don't think I am saying anything we don't already know. The US is at war with China and sees the need to fund the foundries and packaging and will continue to pay. India sees the need to have their own capability, and so do France and Germany (it's not clear if the EU will stay intact).

 

[IanD]

Like it or not, I don't think I am saying anything we don't already know. The US is at war with China and sees the need to fund the foundries and packaging and will continue to pay. India sees the need to have their own capability, and so do France and Germany (it's not clear if the EU will stay intact).

I think it's extremely likely that the EU will stay intact, because (almost) all its members clearly understand they're much better off inside than outside -- especially having seen the effects of the Brexit clusterf*ck, most of the voices who were suggesting leaving have gone strangely quiet...

If anything there's more chance of the US separating into red and blue halves given the intense political polarization there... ;-)

 

[cliff]

I cannot see the EU staying together, but I will avoid expanding into that topic, other than speculating on the countries who want certain fabs.

I do not disagree with the US falling apart. We are committing suicide. This is no longer the country I grew up in. I agree with Ron/Rand Paul's views (at least half of the country doesn't). Unfortunately, the game has changed. The US funded China thinking that prosperity would result in a democracy. Even the Russia situation we screwed up on. Russia and China were enemies for centuries. The US and Russia should have been natural partners, but we pushed Russia to allay with China. We have done something similar with the Saudis.

There are lots of variables in control of dumb and/or corrupt people in most countries. Nationalism is expanding. Half the Western culture is in favor of it, half wants globalism. It is what it is.

 

[Paul2]

There are lots of variables in control of dumb and/or corrupt people in most countries. Nationalism is expanding. Half the Western culture is in favor of it, half wants globalism. It is what it is.

I seen a lot of baseless fatalism going around caucuses.

Whether there are any variables in control of "dumb and/or corrupt people in most countries," it makes no difference to Russian war effort scheduled to crumble if will deny them manganese. Whether they will be allying with China, or not makes no difference to that, and many other things, and how much they are dependent on the West for every living convenience, and industrial item.

It's all up to the executive if we are to go after them for real. Just seeing such obvious leverages not being used yet, means people on the hill are still not serious about it all.

 

[Fred Chen]

I would agree that this structure seems more apt to 3D. However my understanding is that as previously mentioned the complex metal layouts for logic make this very difficult. VTFETs become strongly limited by metal pitches, whereas HNS are more so limited by the transistors themselves. Maybe the thought process is that when we get to 2D materials 3D stacking becomes much simpler than current/near future HNS nodes.

CFETs presume buried interconnect for the lower GAA (n or p)? Otherwise some of the gate pitch would be needed for separate contacts to n and p.

 

[Fred Chen]

VTFET will need very dense metal because transistors themselves will be placed even more dense. And same for stacked VTFETs. HNS will be obviously bigger in horizontal dimension

The vertical channel FETs definitely need the buried contact/interconnect.

 

[blueone]

I highly doubt this will matter. In the case we will go to war against China, the lack of artillery shells will be a much deadlier threat than lack of chips, which can be stocked in great amounts. I.E. total physical chips volume of F35 programme is still less than one 300m wafer.

I agree with the first part of your sentence, but how did you calculate the chip volume needs of F35 production? Aren't there hundreds of chips per plane, of various types?

 

[Paul2]

I agree with the first part of your sentence, but how did you calculate the chip volume needs of F35 production? Aren't there hundreds of chips per plane, of various types?

There are 800 F35s made, with 300mm wafer having around 60000mm² useful area, it's very real that you have 7.5cm² of dies per plane.

Anyways, even if you double, or triple it, you get few wafers per whole run.

 

[benb]

The heated discussion about backside power distribution: Nothing in the articles about how the fab tools change, yet it's relatively clear this is similar to 200mm/300mm transition. Let me explain why.

Currently, a fab tool handles wafers of a certain thickness, from the bottom. Using the backside, you can do all these things, and it's great, but none of the tools in a 16nm fab do this today. So to answer cliff, why this will never happen for 16nm, it requires a new kind of fab that can handle both sides of the wafer. Perhaps we'll call these "600mm fabs" because it's 300mm x 2.

 

[nghanayem]

The heated discussion about backside power distribution: Nothing in the articles about how the fab tools change, yet it's relatively clear this is similar to 200mm/300mm transition. Let me explain why.

Currently, a fab tool handles wafers of a certain thickness, from the bottom. Using the backside, you can do all these things, and it's great, but none of the tools in a 16nm fab do this today. So to answer cliff, why this will never happen for 16nm, it requires a new kind of fab that can handle both sides of the wafer. Perhaps we'll call these "600mm fabs" because it's 300mm x 2.

That's not how it works, and I don't think that processing on both sides of the wafer could ever work.

The process flow is mostly normal until the FS metal are done. Then a donor wafer is attached. The whole thing is then flipped over and the original wafer is thinned down until the nTSVs are revealed. Then you can do the backside metals in a manner that is no different to the front side metals. This process only requires new tools for the wafer thinning, bonding, and potentially for the formation of the nTSVs.

 

[benb]

I know it seems like, sure no problem, two wafers bonded together, epitaxial silicon, but there are few or no 300mm fabs that can handle that. It messes with isolations (no metal in FEOL). It messes with FOUP weight, wafer center of gravity, inspection tool angles, just so many little things. There is zero chance one of those wafers could get through a standard 300mm fab without shattering. That is a weird thing to leave out of an article like that.

 

[nghanayem]

I know it seems like, sure no problem, two wafers bonded together, epitaxial silicon, but there are few or no 300mm fabs that can handle that. It messes with isolations (no metal in FEOL). It messes with FOUP weight, wafer center of gravity, inspection tool angles, just so many little things. There is zero chance one of those wafers could get through a standard 300mm fab without shattering. That is a weird thing to leave out of an article like that.

I never said it was easy. And your right bonding is the hardest step. Besides that there is no reason that existing tools wouldn’t work. I wouldn’t be surprised if wafer handling robots had to be retaught (but that isn’t a big deal). Also you are mistaken, there are in fact metals on the front side. Outside of routing the BPRs up to M0, M1, or the devices themselves the FS BEOL is unchanged. BSPD is a scheme to avoid reducing metal pitches and increase performance. It is not for replacing the FS metal interconnects.