Maybe not totally required at 2nm given it sounds like there will be a node in the N2 family without BSPDN, and TSMC sounds like they are moving to Ru vias. Intel is kind of weird given our recently learned knowledge of 18A being 30nm M0. Presumably this is a scheme to minimize std cell density while keeping single patterning and get extra performance from their transistors (rather than the more conventional approach of using BSPDN only once metal pitches shrink to the limit). I have no clue about Samsung and BSPD though. Given their lower projected density than TSMC/IFS it might not be necessary for 2GAP. Into the nodes that are not yet on public roadmaps, I think you are right that it will be required.
The viability of CFET alternatives?
- Thread starter nghanayem
- Start date
If by DUVish you mean some EUV than maybe (wouldn't bet on it). However DUV will be used extensively for the backside metal stack given the more lax densities above the first couple backside metal layers/nTSVs.
Nothing's ever *absolutely* essential (except EUV for 3nm and below...), but the advantages of BSPDN become pretty strong at 2nm and more so beyond that -- it's not that you can't do 2nm without it, but it's worth the effort even given the cost and difficulty since the wafers will cost a fortune anyway, so the added performance more than makes up for the cost increase.
It would also have advantages at 3nm but the basic process development is done, going back and adding BSPDN would be a major rethink and also take significant time to do -- by the time this could be done 2nm will be there. It's not totally impossible that TSMC might do this for a later member of the 3nm family but it doesn't seem likely, for starters all IP and libraries and tools would need completely redoing.
I think he means "non-EUV processes", in other words 7nm and above.
Correct, 12nm (double patterned) and above. Do I assume rows share met1, then it drills down? EUV technologies are too expensive for my customers, and the number of pads come into play if communicating with HBM. Not having to run power supplies routes throughout is a huge benefit on all processes. The way I see it, why keep squeezing down standard cells if you can't route to them?
You mentioned Skywater's efficiency the other day. They do TSVs on older processes. JMS has a point. He claims there is a huge gap in the middle processes. How about giving your 22-14 some love? You, Fred, etc may have an idea of the difficulty.
You mentioned Skywater's efficiency the other day. They do TSVs on older processes. JMS has a point. He claims there is a huge gap in the middle processes. How about giving your 22-14 some love? You, Fred, etc may have an idea of the difficulty.
This was my assumption too, but I figured I might as well address an alternative interpretation. Even though we will see increasing EUV adoption, we will still see plenty of DUV on these processes (even leading edge nodes will need many of those 600+ DUV tools). Backside metals will be one of the many areas where DUV is still sufficient for. One thing I do wonder is with pellicles becoming more mature and EUV tools becoming more efficient, is if we will ever see EUV single become cheaper than DUV double patterning. I don't think we are there yet, but I do wonder if the E or F will change that (given I think it was the C and upgraded B models that made EUV cheaper than SAQP).
Totally agreed.
OK, let's say TSMC decide to "give their 22-14nm" some love and implement BSPDN. Every single library cell (digital, RAMs, analog) has to be completely redone for layout and re-extracted and simulated -- which also means all the IP in the TSMC ecosystem. Then the process itself has to be developed and qualified. OK, all done -- here's your bill for all the IPs ($millions?), and BTW the wafer cost will be 50% higher -- is that OK? Oh yeah, I forgot, sorry but the IP you want also isn't available, nobody wants to develop it because they don't see the market and they've moved on to newer processes.
It's just not going to happen -- it's like suggesting that a modern EV drivetrain should be retrofitted into a Trabant because that'll make it better.
Which it undoubtedly would, but the problem is that nobody wants an uncomfortable deathtrap cardboard electric car that's also a lot more expensive, they want a Tesla... ;-)
Well then, I guess that is a challenge. I will hang this up in my locker.
Mr. Fred, Mr. Ng, what do you think the TOTAL wafer cost multipliers will be on the 16'ish processes to add the
TSV and backside supply connect up to horizontal met1? Assume a full metal stack of all the bells and whistles. Last I heard, DUV machines are $10M compared to $130M. It seems to me that GF may want to entertain this if TSMC or Intel doesn't. Worth it!
Mr. Fred, Mr. Ng, what do you think the TOTAL wafer cost multipliers will be on the 16'ish processes to add the
TSV and backside supply connect up to horizontal met1? Assume a full metal stack of all the bells and whistles. Last I heard, DUV machines are $10M compared to $130M. It seems to me that GF may want to entertain this if TSMC or Intel doesn't. Worth it!
You're still missing the point -- it's not the equipment cost as such, it's the foundry having the incentive to do all this for a relatively small gain, because 12nm and up doesn't have anything like the power/metal/routing problem that 2nm does.
Changing a process -- not just equipment/flow changes but requalifying it -- is a big step to climb (effort/resource as well as cost), and has to be justified by ROI. I used to work for an IDM with in-house processes, it was difficult enough to get them to change/add anything different even while the process was being developed, and well-nigh impossible after the process was done and qualified.
If adding BSPDN to 12/16nm suddenly opened up a massive new market that wouldn't exist without it then maybe it would happen, but I don't believe this would happen even if you'd like it to... ;-)
GF might be more likely to consider this than TSMC but even then I doubt it -- with 22FDX they did work some time ago on improving the Ft of the PMOS transistors (with process changes) that we would very much like, but they never put it into the production process, presumably because of all the above factors -- basically, not enough demand, recharacterisation, requalification...
What is the benefit to the fab? What is the benefit to the customer?
I'd love to try and see you automatically port an 80+GHz PLL/clock distribution with multiple coupled inductors, since this is difficult enough to do for the designers who know how it works and what everything does... ;-)
(here's a clue to the scale of the problem -- the extracted model for the LC signal/power/GND interconnect is an S-parameter model with >100 ports...)
If you think adding BSPDN to 12/16nm is such a no-brainer, I suggest you talk to the fabs and try and convince them of this. Good luck... ;-)
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Wouldn't know cost multiples. I just know that it adds many new layers, requires a second wafer that needs to be processed, novel tools/techniques for wafer bonding and flipping, and for nodes that have fewer inherent defects it might well have a substantial uptick in failed wafers or defects. My intuition tells me you would get better benefits (way more density and better pref/watt) just moving to N7 for a minimal premium (wouldn't surprise me if it was actually significantly cheaper given N16 already had double patterning).
There are other costs besides 20M for 2 DUV tools. You need extra etch tools, more than 2 photoresist coaters/ovens, stricter design rules/unidirectional rules, and this slows throughout and requires more fab space per wafer start. Per an older paper from Nikon, I think they said DUV double patterning was 2.5-3X more expensive than DUV single.
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Benefit to customer/fab: Unclutter the routing. Stiffer supplies. Fewer supply pads.
Inductors: Nice cherry pick! Of course our optimizer can't do the sizing of inductors (we can make the touchstone=> netlist for converting to transient runs), but how about the rest of the design, like ADCs, phase detectors, charge pumps, etc? We can migrate, then tune individually.
Let's migrate your stuff to the next process node!
Those are "nice-to-haves" -- real benefits mean cheaper, or lower power, or faster, or reduced TTM.
Will it be cheaper than standard 12nm/16nm? No, probably more expensive -- die might be a bit smaller but wafer cost increase is likely to outweigh this. Does it gain a bit of power/speed? Possibly, but see below...
If you want to improve PPA or cost or TTM, 7nm will usually be cheaper for a given function than 12nm with BSPDN, and considerably lower power, and faster, and has a huge IP library, and already exists and is qualified.
If you were Apple and went to a foundry said "If you add BSPDN to 12nm I'll bring you $1B of business that you wouldn't get otherwise" then it might happen. But if the reality was "It'll make my life a bit easier if you spend a lot of effort and money doing this for no extra money for the same business that you'd otherwise get in a different process", it wouldn't even happen for Apple.
But then if your business was big enough to "move the needle" and get a foundry interested, by definition it's big enough that the higher NRE of 7nm can be ignored in favour of smaller die size (lower cost) -- so why use 12nm with BSPDN?
Simple analogue stuff can be automatically ported, but in our experience (on our circuits!) the majority of the analog/mixed-signal design/layout effort goes into the difficult stuff which is *very* hard to port automatically. Your designs may be different, but don't assume that because auto-porting works for you it will work for everyone... ;-)
(FYI I've been looking at analogue synthesis/autoporting for more than 30 years, and we still don't use it...)
Asianometry made a video about the difficulties of 7nm on YouTube. Somebody that represented a foundry confirmed it to me. I was told the yield differences. Based on that, we are sicking with double patterning.
I am not going to convince a fab to do this. I will predict that it will happen. We will see. Our automation works with the present system. If the foundry allows a backside supply connection, we will do that.
You are a critic. I am an implementer.
We have implemented automatic porting between TS40nm <=> GF22 <=> TS16 <=> GF12. We have worked on this for 19 years, and we use it.. We don't synthesize the analog. We just migrate and have different scaling options.
You don't know what you don't know.
As far as qualifications, how tough is that?
Run DRC & LVS on Calibre.
Simulate slopes and Cloads and confirm the liberty file.
Simulate the verilog files vs spice on the logic.
We have our own liberty file generator with timing. We run spice, like everybody else. It isn't magic. Qualifying stdcells... give me a break.
jms_embedded
Active member
I feel like Banquo's ghost here....
You clearly don't have any idea about the consequences of making a change to a process, especially such a major one as adding BSPDN -- which anyone who understands processing will be aware is a huge challenge for all sorts of reasons, otherwise foundries would have done it years ago. They're doing it in 2nm because the pain of not doing it has finally got too much and they need to squeeze more performance improvement over 3nm, not because they really want to. There are still many unresolved issues with BSPDN and the foundries need at least a couple of years to resolve them.
For the foundry, qualification with a major process change like BSPDN isn't just regeneration of libraries, it's the physical qualification of the process itself -- things like metal and via reliability, robustness of ULK dielectrics under stresses including bonding, reliability and defects of wafer bonding processes and TSVs -- and all this has to be done by running multiple trial wafer lots through the fabs and then doing destructive and non-destructive testing of the wafers, and plenty of them. All this takes a lot of time and resource, which is why foundries nowadays are *extremely* reluctant to allow "tweaking" of their processes, unless there's a big business reason to do it (e.g. Apple). I'm involved in just such a discussion with TSMC right now, and even though it's "only" a high-level metal stack change -- *far* simpler and lower risk than BSPDN -- I don't think the chance of them agreeing to do it are good.
On top of this, all the P&R tools need rewriting, the interconnect extraction needs simulation-silicon verification, and all the IP like RAMs needs redoing from scratch -- never mind analog IP like SERDES.
Put all this together, and the chances of BSPDN being retrofitted to anything older than 3nm are zero. Not small, zero. Given the predicted volumes and longevity of 3nm I suspect there is a *tiny* chance of it appearing in one of the later versions of 3nm as a "mid-life kicker" or a "pipe-cleaner" (like EUV was added to N7+, which was an unpopular dead-end process because the layouts were incompatible with N7), though I suspect it's too late and too much effort even for that -- and the killer would most likely be that the relayout needed (*much* worse for BSPDN than N7+) wipes out the IP ecosystem, especially higher-performance IP like 112G/224G SERDES which take a lot of time and effort to deliver, and -- in spite of your claims -- are rather more resistant to auto-porting.
Chances of BSPDN being retrofitted to 12nm -- less than zero... ;-)
"You clearly don't have any idea about the consequences of making a change to a process" That is correct. That is why I am asking the question. I am not a process guy, and there seems to be several knowledgeable guys here. Asking these questions are the purpose of this forum.
While you believe that you are an expert at everything, I am aware of my limitations. I am an analog circuit designer that runs an EDA company. It is a necessity to predict where the industry is headed. The ask the expert forum was made for this. I do not believe that you are the absolute authority. I have worked amongst the best in the industry and have received inputs from them throughout the years. I ask questions, and continue to ask questions. I would like to hear the answers from the process experts, not you.
As far as creating the EDA ecosystems and porting the designs, we have been working on that for 18 years. We rewrite our P&R system all the time. We have completed our 5th rewrite of the system. We learn and improve. If the power supply capability of a process changes, we adapt with it. This is what developers do. We also have our own SerDes design. It is one of the designs we use to prototype the system. We also use ADCs and different styles of PLLs, bandgaps, etc. We migrate untuned with a push of a button, but then tuning is required, followed by trivial compaction and autorouting. While you critique, we do. You do not need to use automation. You can continue to use a shovel while others will use a bulldozer. Your company has an infinite amount of funds. That's great for you. I am working towards helping the tiny companies/entrepreneurs compete in a more practical manner through automation and without the need of having a CAD group nor layout designers.
While you believe that you are an expert at everything, I am aware of my limitations. I am an analog circuit designer that runs an EDA company. It is a necessity to predict where the industry is headed. The ask the expert forum was made for this. I do not believe that you are the absolute authority. I have worked amongst the best in the industry and have received inputs from them throughout the years. I ask questions, and continue to ask questions. I would like to hear the answers from the process experts, not you.
As far as creating the EDA ecosystems and porting the designs, we have been working on that for 18 years. We rewrite our P&R system all the time. We have completed our 5th rewrite of the system. We learn and improve. If the power supply capability of a process changes, we adapt with it. This is what developers do. We also have our own SerDes design. It is one of the designs we use to prototype the system. We also use ADCs and different styles of PLLs, bandgaps, etc. We migrate untuned with a push of a button, but then tuning is required, followed by trivial compaction and autorouting. While you critique, we do. You do not need to use automation. You can continue to use a shovel while others will use a bulldozer. Your company has an infinite amount of funds. That's great for you. I am working towards helping the tiny companies/entrepreneurs compete in a more practical manner through automation and without the need of having a CAD group nor layout designers.
I've been trying to answer your question about adding BSPDN to 12nm, and specifically the issues with process and IP that would result from doing this, based on >30 years of experience talking to foundries about doing such changes -- I've been there many times before with "wouldn't it be nice if the process had [xxx]...". Having had many in-depth discussions with process development teams I'm well aware of all the reasons that this hardly ever happens, even if the foundry is inside your own (IDM) company (which it used to be) -- and as an external foundry customer (yes we're not a small one like you) the chances are even slimmer unless your name begins with A.
You have knowledge about the design side and from there adding BSPDN does of course look wonderful, like many other nice-to-have features. But it's clear from your posts that you have no knowledge about the implications from the foundry side, you just keep saying "of course it will happen" and ignoring cold hard business reality.
There's no point continuing this discussion because you ask a question but don't then want to hear any answer that doesn't agree with your ideas... :-(