The viability of CFET alternatives?

[nghanayem]

There has been much talk around how big of a change GAA is going to be for the eda/design ecosystems. There is also the thought that many folks are probably going to stick with N3 for a good while so they can avoid the worst of the N2 growing pains. I also remember seeing that Samsung said that after GAA, that they could use CFET, negative FET, or VTFET to further scale transistor density. With the above information; are Samsung's hands tied here? IMEC, TSMC, and Intel seem to think that CFET/2D GAA is the way forward. With all of the difficulties of designing for new architectures, is the industry forced to only scale in one manner? CFET seems to offer more opportunities for further scaling than the alternatives, so the loss of VTFET and negative FET isn't that big of a deal. However as an engineer who builds the stuff rather than designs for it, it is sad to see that alternative technologies/techniques can't be allowed to coexist.

 

[Scotten Jones]

CFET is an evolution of horizontal nano sheets so most likely we will see horizontal nano sheets (Samsung multi bridge, Intel Ribbon FET) for a few nodes and then later this decade CFET. Going out into the 2030s stacked 2D layers will likely come in. The semiconductor industry is very risk averse with the size of the investments required and this is the most evolutionary path.

 

[Scotten Jones]

By the way, I say horizontal nano sheets (HNS) because GAA is a more generic term, in fact VFETs if ever used will likely be GAA as well. I don’t think we will see VFETs because they don’t have the long incremental scaling path that HNS do.

 

[nghanayem]

My thoughts exactly. Which is a bit of a shame. Even if it makes sense from a practical perspective. Good catch on the GAA thing. I’ll have to tighten up my language when I’m talking about multiple different GAA technologies in the future.

 

[jms_embedded]

The semiconductor industry is very risk averse with the size of the investments required and this is the most evolutionary path.

I've noticed that risk aversion to new technology. It's kind of weird (at first glance), given that the semiconductor industry relies on someone having proven new technology. Off-topic for this thread, but I would love to hear you expound more on the topic of risk aversion and how some of these high-cost decisions are made. It finally paid off for ASML on EUV, so occasionally someone takes risks.

 

[nghanayem]

It finally paid off for ASML on EUV, so occasionally someone takes risks.

I would say the industry didn't take any risks (maybe excluding Samsung). Intel made the logical choice that EUV wouldn't be ready in 2016/7. TSMC only inserted EUV into 7nm after it was ready for HVM at like one or two layers. I suppose you could say TSMC took a slight risk by not shrinking 7nm into the quad patterning regime because they were under the assumption that limited EUV would be ready sometime during the life of 7nm. Samsung more aggressively integrated EUV at the same time that the original N7 came out, and paid dearly for it. Yields weren't great and throughput/wafer costs were terrible.

 

[cliff]

Speaking in terms of the USERS of the foundry and packaging:

Weak engineers are afraid of making changes. Hardware designers got weaker starting in the mid 90's. They rely on EDA tools to do everything. They are tool jockeys. Young engineers believe Cadence invented the electron. In believe the electron was invented at least 10 years before Cadence.

High cost decisions are sometimes made by short term thinkers (and cowards) who want to keep their jobs for 1 more year.

Any engineer who says "if it ain't broke, don't fix it" should not be considered an engineer.

Anybody can design a bridge that is standing. Only an engineer can design a bridge that is just barely standing.

 

[Mirko Vukovic]

CFET is an evolution of horizontal nano sheets so most likely we will see horizontal nano sheets (Samsung multi bridge, Intel Ribbon FET) for a few nodes and then later this decade CFET. Going out into the 2030s stacked 2D layers will likely come in. The semiconductor industry is very risk averse with the size of the investments required and this is the most evolutionary path.

I see NanoSheet to CFET transition more than a gradual transition - stacking transistors on top of each other presents new opportunities (in terms of interconnects) and challenges (at least doubling of the power density to be dissipated) that will have reprecussions on the whole design change. But, also, I learned not to understimate the engineers that will need to overcome them.

 

[cliff]

I would expect TSMC to keep their foot on the gas pedal. The US will continue to use the printing press, lie about the real inflation rate, and pay whatever TSMC demands in the future. Satellites, drones, and missiles need sophisticated chips, and we are at war. Necessity is the mother of invention.

 

[cliff]

330nm was our last node. No way we can deal with less than 3.3v.

Hey, what's this dual gate stuff (anyway)? Ok, let's go to .25u.

... 90nm? We can't deal with these crazy density rules. Fuhgeddaboudit! Oh, the yields are that good? Well... OK.

28nm... the leakage sucks! We shouldn't have listened to you.

Finfets? You foundry guys are crazy. Forbidden zones? What that hell? It's gonna take years to automate that... OK...finally done.

Now you are telling me skyscraper FETs? OK. I learned my lesson. TSMC, you build it and we will follow (JMS not included). Mr. Blue, Morris can have whatever attitude he wants. He earned it.

 

[Paul2]

By the way, I say horizontal nano sheets (HNS) because GAA is a more generic term, in fact VFETs if ever used will likely be GAA as well. I don’t think we will see VFETs because they don’t have the long incremental scaling path that HNS do.

Few years ago, I was thinking of the opposite. VTFET in naturally a GAA structure, and I was surprised that HNS was chosen instead of leapfrogging to VTFET.

VTFET — is the necessary pre-requisite for monolithic 3D, as much of mono 3D cells are based on elongated VTFET structures. Making a complimentary VTFET is also trivial in comparison to doing it in 2D.

 

[Paul2]

I see NanoSheet to CFET transition more than a gradual transition - stacking transistors on top of each other presents new opportunities (in terms of interconnects) and challenges (at least doubling of the power density to be dissipated) that will have reprecussions on the whole design change. But, also, I learned not to understimate the engineers that will need to overcome them.

Current FinFETs are sitting comfortably very close to the "wall" of 100W/cm² at 3-5ghz.

A change to CFET will mean more transistors, lower frequencies, more relaxed clocking. Something similar the time when Intel went to first FinFETs.

CFET SRAM would be the most interesting use of CFET.

 

[nghanayem]

Few years ago, I was thinking of the opposite. VTFET in naturally a GAA structure, and I was surprised that HNS was chosen instead of leapfrogging to VTFET.

VTFET — is the necessary pre-requisite for monolithic 3D, as much of mono 3D cells are based on elongated VTFET structures. Making a complimentary VTFET is also trivial in comparison to doing it in 2D.

I would agree that this structure seems more apt to 3D. However my understanding is that as previously mentioned the complex metal layouts for logic make this very difficult. VTFETs become strongly limited by metal pitches, whereas HNS are more so limited by the transistors themselves. Maybe the thought process is that when we get to 2D materials 3D stacking becomes much simpler than current/near future HNS nodes.

 

[Paul2]

I would agree that this structure seems more apt to 3D. However my understanding is that as previously mentioned the complex metal layouts for logic make this very difficult. VTFETs become strongly limited by metal pitches, whereas HNS are more so limited by the transistors themselves. Maybe the thought process is that when we get to 2D materials 3D stacking becomes much simpler than current/near future HNS nodes.

VTFET will need very dense metal because transistors themselves will be placed even more dense. And same for stacked VTFETs. HNS will be obviously bigger in horizontal dimension

 

[Tanj]

Current FinFETs are sitting comfortably very close to the "wall" of 100W/cm² at 3-5ghz.

The wall for liquid coolant flowing within the package directly over the chip, including directly etched coolant channels or fins, may be around 1kW/cm2.

The other way to go is design the CMOS with band gaps and other changes to operate at liquid N2, for a net efficiency multiplier even taking chiller inefficiency into account. See IEDM22 session 23.5.

Combine both for the win.

 

[IanD]

VTFET will need very dense metal because transistors themselves will be placed even more dense. And same for stacked VTFETs. HNS will be obviously bigger in horizontal dimension

This is one reason why backside power is pretty much essential at 2nm and below, the fine-pitch metal for signals is then above the FETs and the high-current coarse-pitch metal for power is below them. This avoids the need to get the power down past the thin high-resistance signal routing layers, so greatly lowers power mesh resistance as well as increasing density.

 

[cliff]

Anybody have predictions of backside power availablity on DUV'ish processes?

 

[IanD]

Anybody have predictions of backside power availablity on DUV'ish processes?

Never... ;-)

 

[cliff]

The ASML CEO predicted that by 2025 they will produce 90 EUV machines and 660 DUV machines (something like that). Having the backside supply connection frees up a lot of routing, as you said, as well as tighten up the supply. This would benefit all processes. Seems like this is pretty good bang for the buck. Any predictions process guys?

 

[IanD]

The ASML CEO predicted that by 2025 they will produce 90 EUV machines and 660 DUV machines (something like that). Having the backside supply connection frees up a lot of routing, as you said, as well as tighten up the supply. This would benefit all processes. Seems like this is pretty good bang for the buck. Any predictions process guys?

The bigger geometry processes don't have such big routing/metal density/voltage drop problems as 2nm and below. Adding backside power (and the TSVs and wafer bonding/thinning and...) is not easy or cheap and needs a lot of process change/infrastructure/qualification, no foundry is going to do it on an older process where the wafer cost is much lower and the benefits are much smaller.