There has been much talk around how big of a change GAA is going to be for the eda/design ecosystems. There is also the thought that many folks are probably going to stick with N3 for a good while so they can avoid the worst of the N2 growing pains. I also remember seeing that Samsung said that after GAA, that they could use CFET, negative FET, or VTFET to further scale transistor density. With the above information; are Samsung's hands tied here? IMEC, TSMC, and Intel seem to think that CFET/2D GAA is the way forward. With all of the difficulties of designing for new architectures, is the industry forced to only scale in one manner? CFET seems to offer more opportunities for further scaling than the alternatives, so the loss of VTFET and negative FET isn't that big of a deal. However as an engineer who builds the stuff rather than designs for it, it is sad to see that alternative technologies/techniques can't be allowed to coexist.