Tom Dillinger
Member
I recently came across an interesting technical article, with a current interpretation of the infamous RISC vs. CISC instruction set architecture debate, which has been ingrained in the computer science field for over 25 years. A link to the article is here.
The paper provides a good background on the origins of the debate, followed by a thorough analysis of several x86 and ARM designs, targeted for different power/performance tradeoffs. The authors try to normalize their results for these different targets.
Their conclusion is that advances in compute architecture and compiler optimization technology over time have rendered the ISA debate rather moot. For general workloads, they assert that the specific ISA is not the key differentiator – other microarchitectural details are much more important in establishing the power/performance/cost design point. They highlight the use of “micro-ops” to execute complex instructions, the I-cache architecture in current core designs, etc.
Would you agree? Although x86 is no doubt the best example of a current CISC implementation, is their analysis skewed by the omission of MIPS, Power, and SPARC in their RISC repertoire?
This conclusion sheds an interesting light on the “ARM-based (micro)servers will naturally be more efficient” market, IMHO.
-chipguy
The paper provides a good background on the origins of the debate, followed by a thorough analysis of several x86 and ARM designs, targeted for different power/performance tradeoffs. The authors try to normalize their results for these different targets.
Their conclusion is that advances in compute architecture and compiler optimization technology over time have rendered the ISA debate rather moot. For general workloads, they assert that the specific ISA is not the key differentiator – other microarchitectural details are much more important in establishing the power/performance/cost design point. They highlight the use of “micro-ops” to execute complex instructions, the I-cache architecture in current core designs, etc.
Would you agree? Although x86 is no doubt the best example of a current CISC implementation, is their analysis skewed by the omission of MIPS, Power, and SPARC in their RISC repertoire?
This conclusion sheds an interesting light on the “ARM-based (micro)servers will naturally be more efficient” market, IMHO.
-chipguy