Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/the-nanosheet-transistor-is-the-next-and-maybe-last-step-in-moore%E2%80%99s-law.12864/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/JobRunner] => 1030170
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000670
            [ThemeHouse/XPress] => 1010394
            [XF] => 2011072
            [XFI] => 1030270
        )

    [wordpress] => /var/www/html
)

The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore’s Law

Daniel Nenni

Admin
Staff member
Great read but I think 2021 is a bit optimistic:

The Shape of Things to Come: Nanosheet field-effect transistors flow current through multiple stacks of silicon that are completely surrounded by the transistor gate. The design reduces avenues for current to leak through and boosts the amount of current the device can drive.

Nanosheet.jpeg


Snip......

The FinFET has no doubt been a great success. Though it was invented more than a decade earlier, the FinFET was first commercially introduced in 2011 at the 22-nm node by Intel and later by Samsung, TSMC, and others. Since then it’s been the workhorse of cutting-edge silicon logic in these final stages of Moore’s Law scaling. But all good things come to an end.

With the 3-nm node, FinFETs are not up to the task. The three of us saw this coming in one form or another more than a decade ago, as did others.

Excellent as it is, the FinFET has its problems. For one, it introduced a design limitation that wasn’t a factor for the old “planar” transistor. To see the problem, you have to understand that there’s always a trade-off among a transistor’s speed, power consumption, manufacturing complexity, and cost. And that trade-off has a lot to do with the width of the channel, which is called Weff in device-design circles. More width means you can drive more current and switch a transistor on and off faster. But it also requires a more complicated, costly manufacturing process.

In a planar device, you can make this trade-off simply by adjusting the geometry of the channel. But fins don’t allow as much flexibility. The metal interconnects that link transistors to form circuits are built in layers above the transistors themselves. Because of this, the transistor fins can’t really vary very much in height—equivalent to width in planar designs—without interfering with the interconnect layers. Today, chip designers get around this problem by making individual transistors that have multiple fins.

Another of the FinFET’s shortcomings is that its gate surrounds the rectangular silicon fin on only three sides, leaving the bottom side connected to the body of the silicon. This allows some leakage current to flow when the transistor is off. Many researchers reasoned that to gain ultimate control over the channel region, the gate needed to surround it completely.

 

Arthur Hanson

Well-known member
Dan, what do you think the impact of SOFI will be on the industry. Also do you think SOFI will have room for constant advancement like other processes or will quickly hit a dead end ? Also do you think SOFI will be stacked in interfaced layers mixing different processes? Any other thoughts on this would also be appreciated. Thanks
 

Portland

Member
It's a new meaning and very old meaning for "architecture" for logic circuits. It's only the beginning for something new.

I do wish I was a part of this some days.
 
Top