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The Intel (INTC) CEO Pat Gelsinger on Q1 2021 Results Discussion

Daniel Nenni

Admin
Staff member
Patrick_Gelsinger_ML40.jpg


Just a couple of comments on Pat's introduction:

"The unprecedented demand for semiconductors has stressed supply chains across the industry. We have doubled our internal wafer capacity the last few years, but the industry is now challenged by a shortage of foundry capacity, substrates and components."

To be perfectly clear, there is no shortage of foundry capacity. Unfortunately this false narrative is a net positive for the semiconductor ecosystem so it will continue for as long as we let it. Foundries can now throw billions of dollars of CAPEX at capacity with impunity. Even governments around the world can now justify the type of investment in the semiconductor ecosystem that China has been making for the past 10+ years.

Due to "shortages" CEOs all over the world now have an excuse for bad management. "It's not my fault, it's the semiconductor shortage!" Always handy to have a ready made excuse in your back pocket.

Bottom line: TSMC will be the big winner here. TSMC builds the most cost effective semiconductor manufacturing capacity in the world, hands down. Do you think Samsung would survive in the foundry business if they charged more than TSMC per wafer? Not even close. The foundry business is all about cost and no foundry today can match TSMC at the leading edge, absolutely. So what happens when foundry capacity bubbles as a results of all this spending? Only the financially fit will thrive and that is TSMC and Samsung, my opinion.

"It’s clear the industry and Intel will need more capacity to meet strong future demand, which is why we are dramatically expanding our foundry capability with Intel Foundry Services, starting with a $20 billion investment for our first large scale foundry operations in Arizona. We plan to expand other locations and establish Intel Foundry Services as a major provider of committed foundry capacity in the U.S. and Europe, while ensuring a sustainable and secure semiconductor supply for the world."

Again, but at what cost to the foundry customers? And don't forget about TRUST. Careers and companies are on the line when you commit to a foundry and that foundry MUST deliver. Intel has not delivered in the foundry business in the past and today Intel has not delivered on leading edge process technology roadmaps. Trust must be earned by actions, not promises.

"Since its announcement, the industry response to Intel Foundry Services have already been incredible. We are engaged with well over 50 potential customers today. We are seeing excitement from some of the top technology giants in the world across industry verticals ranging from automotive to high-performance compute and cloud service providers."

Deja vu of the last time Intel went into the foundry business. And "seeing excitement" is not the same as getting customer orders. Of course customers are excited about having another foundry source. Who wouldn't be? I certainly am. And if the Intel CEO called would you not be excited? But that excitement is a VERY long way to earning trust and more importantly making money in the foundry business.

"With IDM 2.0, we will have superior capacity and supply, resilience by leveraging our internal and external capacity and a superior cost structure."

Now this is true with TSMC as a partner for external capacity. Unfortunately that will put the internal Intel IDM technology/capacity under a magnifying glass and if it is not competitive with what TSMC provides? Certainly a bet Pat is willing to make because he really does not have a choice in my opinion.

"Within the next couple of weeks, we will tape in the compute tile for Meteor Lake, our first 7-nanometer CPU for 2023."

Tape in? We have called it a tape-out since the beginning of time, back when designs were stored on magnetic tape. When a design is finished you streamed the GDS file out and send the magnetic tape to manufacturing. There is no "taping in". Major technology foul in my opinion.

Compute tile? I think he means chiplet. Just like Intel Trigate is really a finFET. Gotta love marketing people. full SoC, GPU, CPU, and AI chips will be taping-out at TSMC 3N this year so I hope Intel has more than a 7nm chiplet coming in 2021.

The real question is how many 7nm products can Intel ship in 2023? Will 7nm wafers dribble out in 2023 due to constrained EUV throughput and/or low yields? Apple will be the first to TSMC 3nm (which has a density edge over Intel 7nm) and that means TSMC will be in 3nm HVM in 2H 2022.

So what is Intel's TSMC 3nm plan? TSMC 3nm tape ins? Where is the transparency here? Are Intel's TSMC 3nm based chips ahead of Intel's 7nm?

"Given the incredible demand for computing, the strength of our IDM 2.0 strategy and the technology investments we are making, I am certain Intel’s best days are in front of us."

I certainly hope so. Not much in the Q&A unless I missed something?

Reference:

 
Last edited:

Piefkee

New member
Daniel there is no real plan to Go big on TSMC for Intel. Its just PR for investers...ecerything that is not a CPU could go to TSMC...
 

Daniel Nenni

Admin
Staff member
Daniel there is no real plan to Go big on TSMC for Intel. Its just PR for investers...ecerything that is not a CPU could go to TSMC...

One rumor was that Bob Swan did in fact plan on going big with TSMC (Thus the TSMC CAPEX hike last year) to light the competitive fire under Intel manufacturing, and Bob got fired for it. So yes, you are probably right, with Pat it will be limited. Personally I thought all battery operated products would have TSMC silicon inside. I was even going to make up "TSMC Inside" stickers for my local electronics outlet.
 

lilo777

Member
View attachment 443

Just a couple of comments on Pat's introduction:

"The unprecedented demand for semiconductors has stressed supply chains across the industry. We have doubled our internal wafer capacity the last few years, but the industry is now challenged by a shortage of foundry capacity, substrates and components."

To be perfectly clear, there is no shortage of foundry capacity. Unfortunately this false narrative is a net positive for the semiconductor ecosystem so it will continue for as long as we let it. Foundries can now throw billions of dollars of CAPEX at capacity with impunity. Even governments around the world can now justify the type of investment in the semiconductor ecosystem that China has been making for the past 10+ years.

Due to "shortages" CEOs all over the world now have an excuse for bad management. "It's not my fault, it's the semiconductor shortage!" Always handy to have a ready made excuse in your back pocket.

Bottom line: TSMC will be the big winner here. TSMC builds the most cost effective semiconductor manufacturing capacity in the world, hands down. Do you think Samsung would survive in the foundry business if they charged more than TSMC per wafer? Not even close. The foundry business is all about cost and no foundry today can match TSMC at the leading edge, absolutely. So what happens when foundry capacity bubbles as a results of all this spending? Only the financially fit will thrive and that is TSMC and Samsung, my opinion.

"It’s clear the industry and Intel will need more capacity to meet strong future demand, which is why we are dramatically expanding our foundry capability with Intel Foundry Services, starting with a $20 billion investment for our first large scale foundry operations in Arizona. We plan to expand other locations and establish Intel Foundry Services as a major provider of committed foundry capacity in the U.S. and Europe, while ensuring a sustainable and secure semiconductor supply for the world."

Again, but at what cost to the foundry customers? And don't forget about TRUST. Careers and companies are on the line when you commit to a foundry and that foundry MUST deliver. Intel has not delivered in the foundry business in the past and today Intel has not delivered on leading edge process technology roadmaps. Trust must be earned by actions, not promises.

"Since its announcement, the industry response to Intel Foundry Services have already been incredible. We are engaged with well over 50 potential customers today. We are seeing excitement from some of the top technology giants in the world across industry verticals ranging from automotive to high-performance compute and cloud service providers."

Deja vu of the last time Intel went into the foundry business. And "seeing excitement" is not the same as getting customer orders. Of course customers are excited about having another foundry source. Who wouldn't be? I certainly am. And if the Intel CEO called would you not be excited? But that excitement is a VERY long way to earning trust and more importantly making money in the foundry business.

"With IDM 2.0, we will have superior capacity and supply, resilience by leveraging our internal and external capacity and a superior cost structure."

Now this is true with TSMC as a partner for external capacity. Unfortunately that will put the internal Intel IDM technology/capacity under a magnifying glass and if it is not competitive with what TSMC provides? Certainly a bet Pat is willing to make because he really does not have a choice in my opinion.

"Within the next couple of weeks, we will tape in the compute tile for Meteor Lake, our first 7-nanometer CPU for 2023."

Tape in? We have called it a tape-out since the beginning of time, back when designs were stored on magnetic tape. When a design is finished you streamed the GDS file out and send the magnetic tape to manufacturing. There is no "taping in". Major technology foul in my opinion.

Compute tile? I think he means chiplet. Just like Intel Trigate is really a finFET. Gotta love marketing people. full SoC, GPU, CPU, and AI chips will be taping-out at TSMC 3N this year so I hope Intel has more than a 7nm chiplet coming in 2021.

The real question is how many 7nm products can Intel ship in 2023? Will 7nm wafers dribble out in 2023 due to constrained EUV throughput and/or low yields? Apple will be the first to TSMC 3nm (which has a density edge over Intel 7nm) and that means TSMC will be in 3nm HVM in 2H 2022.

So what is Intel's TSMC 3nm plan? TSMC 3nm tape ins? Where is the transparency here? Are Intel's TSMC 3nm based chips ahead of Intel's 7nm?

"Given the incredible demand for computing, the strength of our IDM 2.0 strategy and the technology investments we are making, I am certain Intel’s best days are in front of us."

I certainly hope so. Not much in the Q&A unless I missed something?

Reference:

I don't know much about this stuff but I can confirm that the "tape out" term was replaced with "tape in" quite a while ago. I am curious as to the reasons.

As far as chiplets vs tiles terminology is concerned I believe there are important technical differences between the two (at least from Intel point of view). Obviously both represent individual dies. The difference is in interconnect. Here is an article explaining the difference.
 

Daniel Nenni

Admin
Staff member
I don't know much about this stuff but I can confirm that the "tape out" term was replaced with "tape in" quite a while ago. I am curious as to the reasons.

As far as chiplets vs tiles terminology is concerned I believe there are important technical differences between the two (at least from Intel point of view). Obviously both represent individual dies. The difference is in interconnect. Here is an article explaining the difference.

You learn something new everyday here on SemiWiki.com:

"Tape-out is the final phase of a design life cycle for a IC design (ASIC/SOC) before the manufacturing starts. (And the same for a PCB design before it is manufactured). This is the phase when the final database that contains the design information is sent to a foundry to begin the manufacturing process. The data base will be in GDSII format. The term tape-out was named so because historically a magnetic tape was used to store all the ASIC design files and this tape was then send to the foundry for manufacturing.

A tape-in is a relatively newer terminology used by certain companies that are involved in bigger SOC (System on Chip) designs that involves integration of several IPs. Some of these organizations will have different groups (and even business units) that work on different IP designs and these are then integrated to a top level SOC design which is finally taped out for manufacturing. When each of the IP groups are ready with their final data base, they tape-in their data base to the top level design team which finally makes a tape-out of full design database to the foundry."

Yes, we were briefed on Intel tiles last week. A detailed article will be out soon. Yes there are some interconnect differences but that does not make it a tile versus a chiplet. Both are marketing terms, and again, one will be an industry standard term and the other will not, just my opinion of course.
 

Moshe Zalcberg

Moderator
Daniel, good discussion, thanks for posting.
However, many of these topics are long term. What puzzles me the most is Pat's short-term strategy on automotive.
On one hand, he repeated the 4 areas of interest he mentioned when he stepped in: "There are four super powers driving digital transformation, cloud, connectivity, artificial intelligence and the intelligent edge. " Is auto "intelligent edge"?
On the other hand, Mobileye had a "all-time record" but $377 million revenue is not that much in the big scale of Intel.
And still, Pat said a couple of weeks ago that he will be producing chips for automakers within 6-9 months.
I guess automotive process is not where you start when even your own automotive products are reportedly fabed at TSMC?

 

Andy1299

New member
See
View attachment 443

Just a couple of comments on Pat's introduction:

"The unprecedented demand for semiconductors has stressed supply chains across the industry. We have doubled our internal wafer capacity the last few years, but the industry is now challenged by a shortage of foundry capacity, substrates and components."

To be perfectly clear, there is no shortage of foundry capacity. Unfortunately this false narrative is a net positive for the semiconductor ecosystem so it will continue for as long as we let it. Foundries can now throw billions of dollars of CAPEX at capacity with impunity. Even governments around the world can now justify the type of investment in the semiconductor ecosystem that China has been making for the past 10+ years.

Due to "shortages" CEOs all over the world now have an excuse for bad management. "It's not my fault, it's the semiconductor shortage!" Always handy to have a ready made excuse in your back pocket.

Bottom line: TSMC will be the big winner here. TSMC builds the most cost effective semiconductor manufacturing capacity in the world, hands down. Do you think Samsung would survive in the foundry business if they charged more than TSMC per wafer? Not even close. The foundry business is all about cost and no foundry today can match TSMC at the leading edge, absolutely. So what happens when foundry capacity bubbles as a results of all this spending? Only the financially fit will thrive and that is TSMC and Samsung, my opinion.

"It’s clear the industry and Intel will need more capacity to meet strong future demand, which is why we are dramatically expanding our foundry capability with Intel Foundry Services, starting with a $20 billion investment for our first large scale foundry operations in Arizona. We plan to expand other locations and establish Intel Foundry Services as a major provider of committed foundry capacity in the U.S. and Europe, while ensuring a sustainable and secure semiconductor supply for the world."

Again, but at what cost to the foundry customers? And don't forget about TRUST. Careers and companies are on the line when you commit to a foundry and that foundry MUST deliver. Intel has not delivered in the foundry business in the past and today Intel has not delivered on leading edge process technology roadmaps. Trust must be earned by actions, not promises.

"Since its announcement, the industry response to Intel Foundry Services have already been incredible. We are engaged with well over 50 potential customers today. We are seeing excitement from some of the top technology giants in the world across industry verticals ranging from automotive to high-performance compute and cloud service providers."

Deja vu of the last time Intel went into the foundry business. And "seeing excitement" is not the same as getting customer orders. Of course customers are excited about having another foundry source. Who wouldn't be? I certainly am. And if the Intel CEO called would you not be excited? But that excitement is a VERY long way to earning trust and more importantly making money in the foundry business.

"With IDM 2.0, we will have superior capacity and supply, resilience by leveraging our internal and external capacity and a superior cost structure."

Now this is true with TSMC as a partner for external capacity. Unfortunately that will put the internal Intel IDM technology/capacity under a magnifying glass and if it is not competitive with what TSMC provides? Certainly a bet Pat is willing to make because he really does not have a choice in my opinion.

"Within the next couple of weeks, we will tape in the compute tile for Meteor Lake, our first 7-nanometer CPU for 2023."

Tape in? We have called it a tape-out since the beginning of time, back when designs were stored on magnetic tape. When a design is finished you streamed the GDS file out and send the magnetic tape to manufacturing. There is no "taping in". Major technology foul in my opinion.

Compute tile? I think he means chiplet. Just like Intel Trigate is really a finFET. Gotta love marketing people. full SoC, GPU, CPU, and AI chips will be taping-out at TSMC 3N this year so I hope Intel has more than a 7nm chiplet coming in 2021.

The real question is how many 7nm products can Intel ship in 2023? Will 7nm wafers dribble out in 2023 due to constrained EUV throughput and/or low yields? Apple will be the first to TSMC 3nm (which has a density edge over Intel 7nm) and that means TSMC will be in 3nm HVM in 2H 2022.

So what is Intel's TSMC 3nm plan? TSMC 3nm tape ins? Where is the transparency here? Are Intel's TSMC 3nm based chips ahead of Intel's 7nm?

"Given the incredible demand for computing, the strength of our IDM 2.0 strategy and the technology investments we are making, I am certain Intel’s best days are in front of us."

I certainly hope so. Not much in the Q&A unless I missed something?

Reference:

Thanks Daniel! Really appreciate the insight around IFS and chiplets/ tiles. As I think more and more about IFS I’m coming to the opinion that it less grand than we all thought at the beginning. I.e it’s looking more and more like it’s 80% about custom x86 for hyperscalers and 20% true foundry for automotive etc.. furthermore the custom x86 is looking like it is very close to what intel does today for hyperscalers vs. true licensing/ customer led design. The fact that government funding is involved makes me believe that they promoted the foundry stuff more than they would have to get funding for the x86 customization they are already doing. Intel already has a lot of money but as a value stock it also has less room to maneuver.

one additional thought on shortages. Is I that TSMC may even grow share during the “shortage”. They are the top customer to virtually every material and machine supplier (euv included) and if you are a supplier you always prioritize extra orders from your top customer first. You just do.
 

lilo777

Member
Daniel, good discussion, thanks for posting.
However, many of these topics are long term. What puzzles me the most is Pat's short-term strategy on automotive.
On one hand, he repeated the 4 areas of interest he mentioned when he stepped in: "There are four super powers driving digital transformation, cloud, connectivity, artificial intelligence and the intelligent edge. " Is auto "intelligent edge"?
On the other hand, Mobileye had a "all-time record" but $377 million revenue is not that much in the big scale of Intel.
And still, Pat said a couple of weeks ago that he will be producing chips for automakers within 6-9 months.
I guess automotive process is not where you start when even your own automotive products are reportedly fabed at TSMC?

I do not think they mean Mobileye chips when people talk about automotive chips. Those are AI chips. They alsohave sensors but I have no idea who manufactures those (probably not TSMC). The reason Mobileye and some other Intel subsidiaries/groups use TSMC is because they were acquired by Intel and their design teams had established design flows for TSMC. In some cases they may want to use the advantages TSMC process/IP offer. This is probably unimportant for typical automotive chips which use mature (old) tech process. I am sure Intel is talking about automotive chips because that's what in the news and they (as well as others) are lobbying for government money.
 

Jumper

New member
The big investments that Intel is making look pale in comparison to TSMC that is making absolutely gigantic investments that will just solidify it's position in the upcoming years. Intel's financial side isn't that great either. They have pretty big debt and I think that they will have to make more buybacks if they want to keep stock at reasonable levels. Also the biggest problem for Intel is huge competition in server market. And lastly the manufacturing capabilities of AMD and Nvidia on 5nm and 3nm will be huge considering the investments TSMC is making.
 

Eric Esteve

Moderator
I don't know much about this stuff but I can confirm that the "tape out" term was replaced with "tape in" quite a while ago. I am curious as to the reasons.

As far as chiplets vs tiles terminology is concerned I believe there are important technical differences between the two (at least from Intel point of view). Obviously both represent individual dies. The difference is in interconnect. Here is an article explaining the difference.
From this article you mention: "going from one chiplet to another requires a bus, whereas that's not the case with Intel's tile design."...
it doesn't really help! How do you go from one chiplet to another, if not by using interconnect, parallel bus with clock forwarded or SerDes with embedded clock?
 

count

Active member
Reminds me of "It's not FinFet it's Intel TriGate(TM)", but with a key difference that Intel is no longer a technology leader.

Intel trying to sound like their solution is differentiated, and maybe that worked when Intel was the trendsetter, but now that they are no longer the leader they just sound like they have no idea what they are doing. The entire industry settled on the term chiplet literally years ago, so when Intel comes in from behind and tries to rebrand them as Intel Tiles, it's forced and weak messaging.
 

Daniel Nenni

Admin
Staff member
Daniel, good discussion, thanks for posting.
However, many of these topics are long term. What puzzles me the most is Pat's short-term strategy on automotive.
On one hand, he repeated the 4 areas of interest he mentioned when he stepped in: "There are four super powers driving digital transformation, cloud, connectivity, artificial intelligence and the intelligent edge. " Is auto "intelligent edge"?
On the other hand, Mobileye had a "all-time record" but $377 million revenue is not that much in the big scale of Intel.
And still, Pat said a couple of weeks ago that he will be producing chips for automakers within 6-9 months.
I guess automotive process is not where you start when even your own automotive products are reportedly fabed at TSMC?


I was hoping it was a miscommunication. I see no way for Intel to get their processes automotive certified and get chips out in 6-9 months.
 

hkwint

Member
Daniel, good discussion, thanks for posting.
However, many of these topics are long term. What puzzles me the most is Pat's short-term strategy on automotive.
On one hand, he repeated the 4 areas of interest he mentioned when he stepped in: "There are four super powers driving digital transformation, cloud, connectivity, artificial intelligence and the intelligent edge. " Is auto "intelligent edge"?

For Intel, chips which go into automotive vehicles is IoT.
Intel doesn't have IoT the way the rest of the world defines it.

IoT usually means, low energy chips of a few cents. Those have ARM, MIPS, Andes, RISC-V cores. No x86.
The way I understood it, but I may be wrong; is that Intel shareholders wanted Intel to partake in IoT growth market (Krzaninch nonsense "growing TAM"-promise) ; Intel couldn't compete, Intel left*, so Intel made up their own "proprietary" definition of IoT which is not compatible with the rest of the world.
I even understood, if they sell Xeon's their clients are using it to process sensor date (of ARM-connected sensors), they call it IoT as well.
Apart from that; their "real" IoT portfolio was dying last time I heard; of the development boards (Joule, Edison) several were cancelled.

*https://www.engadget.com/2017-06-20-intel-cancels-galileo-joule-edison.html

On the other hand, Mobileye had a "all-time record" but $377 million revenue is not that much in the big scale of Intel.
And still, Pat said a couple of weeks ago that he will be producing chips for automakers within 6-9 months.
Very well highlighted!
Chips for automakers is not the same as "automotive chips" which actually connect to the car's battery and go _into_ the vehicle.
Let's say some German car brands work together on a mapping service. Cars scan their surroundings with sonar, Lidar, vision, radar, maybe preprocess on some chip, send it to some German datacenter, where the map data is processed on Xeon server cores by the car brands data-center.

Bwham, there you have your "chips for automakers"! Come investor day; investors are curious if Intel is joining (and how much) in the perceived "automotive growth market", so what do you do: Tell everybody you're producing "chips for automakers". Only sane and informed people who don't depend on INTC stock price, will dare to ask what they mean by it, and why on earth they would label server chips as automotive / IoT.
 

hkwint

Member
"Given the incredible demand for computing, the strength of our IDM 2.0 strategy and the technology investments we are making, I am certain Intel’s best days are in front of us."

I certainly hope so. Not much in the Q&A unless I missed something?

Seriously, I wonder about those 'investments', how on earth are they going to pay for it?

As someone who studied the stock movements last few earnings releases; I happened to notice the investment-crowd IMNSHO is focusing on the wrong metrics. DCG Revenue, buyback-engineered EPS: Yawn.

Those who actually read the 10-Q on page 9 however, notice DCG income diminished from $3.50 B to $1.25 B!!!

If you were to extrapolate it for a year; it means 9B less income from DCG.
Yeah; I know; income may be steered by accountants in a certain direction, seasonality, clients consuming the inventory channel etc; but also last few 10-Q earning remarks for CCG made it perfectly clear: 10nm is the end of Intel's ability to both invest in technical leadership _and_ hand out $19B to shareholders.

They will have to choose between either of those two.

But no, instead of choosing one of the two, either surpassing TSMC for CPU fab-processes for Xeons somehow _or_ handing out money to shareholders, they added a third horse, IDM2.0.

That's pure magic! And I'm stunned by their utter brilliance! I didn't know so much rabbits fit in one hat. I must be really dumb, to be questioning their promises.

Which is of course why I shorted in the afternoon (UTC) before INTC ER; only to pivot this coming wednesday; when the usual Intel "friends" in the media and Intel PR will start to "talk" the stock back up. Where it increases next 2,5 months until next ER.

When reality hits again, so called "investors" are shocked the Intel PR was al not real and baked air, and unlike what was promised ("technical leadership"), Intel still didn't catch up with TSMC ("Didn't catch up with AMD" in the words of the investor crowd), the investors are disappointed the hot air balloon leaks and stock price tanks again; because reality doesn't line up with all the PR and SeekingAlpha-shill articles. And three days later, it all starts again.

Has been last three quarterly earnings, this time again, and probably also next time; Swan or Gelsinger, it doesn't matter.
It's all so predictable, I almost feel guilty of earning (in my case as a Mickey Mouse investor, only a few pennies) from it.
 

count

Active member
Seriously, I wonder about those 'investments', how on earth are they going to pay for it?

As someone who studied the stock movements last few earnings releases; I happened to notice the investment-crowd IMNSHO is focusing on the wrong metrics. DCG Revenue, buyback-engineered EPS: Yawn.

Those who actually read the 10-Q on page 9 however, notice DCG income diminished from $3.50 B to $1.25 B!!!

If you were to extrapolate it for a year; it means 9B less income from DCG.
Yeah; I know; income may be steered by accountants in a certain direction, seasonality, clients consuming the inventory channel etc; but also last few 10-Q earning remarks for CCG made it perfectly clear: 10nm is the end of Intel's ability to both invest in technical leadership _and_ hand out $19B to shareholders.

They will have to choose between either of those two.

But no, instead of choosing one of the two, either surpassing TSMC for CPU fab-processes for Xeons somehow _or_ handing out money to shareholders, they added a third horse, IDM2.0.

That's pure magic! And I'm stunned by their utter brilliance! I didn't know so much rabbits fit in one hat. I must be really dumb, to be questioning their promises.

Which is of course why I shorted in the afternoon (UTC) before INTC ER; only to pivot this coming wednesday; when the usual Intel "friends" in the media and Intel PR will start to "talk" the stock back up. Where it increases next 2,5 months until next ER.

When reality hits again, so called "investors" are shocked the Intel PR was al not real and baked air, and unlike what was promised ("technical leadership"), Intel still didn't catch up with TSMC ("Didn't catch up with AMD" in the words of the investor crowd), the investors are disappointed the hot air balloon leaks and stock price tanks again; because reality doesn't line up with all the PR and SeekingAlpha-shill articles. And three days later, it all starts again.

Has been last three quarterly earnings, this time again, and probably also next time; Swan or Gelsinger, it doesn't matter.
It's all so predictable, I almost feel guilty of earning (in my case as a Mickey Mouse investor, only a few pennies) from it.

I think they expect the US government to foot the cost of new fabs in the US. They called the $50b the government is planning to spend as a "downpayment". They have pretty much turned into beggers.
 

hkwint

Member
I think they expect the US government to foot the cost of new fabs in the US. They called the $50b the government is planning to spend as a "downpayment". They have pretty much turned into beggers.
Wow, that's interesting.
Because then in my limited understanding; it would mean US government is helping to keep the buybacks and dividends of billions per year floating, because Intel "on their own merits" can't?

When was Intel actually labeled "too big too fail", to the point where someone in politics greenlighted the bailout of its shareholders?
I'm afraid I missed the memo.
 

Daniel Nenni

Admin
Staff member
From a trusted source:

A chiplet incorporates more complex Tx-to-Rx interface circuitry, enabling the interconnects to be routed over a considerable distance on a 2.5D substrate (silicon interposer or the organic substrate itself). Here's an example from a recent SemiWiki article on a "clock-forwarded interface" for Ultra-Short Reach signaling between chiplets.

Intel Tile.png


A "tile" is an Intel-specific term for die that connect via their EMIB bridge, which is simply a set of interconnect wires between adjacent die, typically limited to less than 8mm in length. It's Intel's way of differentiating how EMIB differs from other 2.5D technologies.

I understand the confusion, though...

On an Intel "tile", not all die connections use the EMIB, of course -- many are routed in the substrate. So, a tile with EMIB is not "all encompassing" when it comes to the interconnect.

And, TSMC recently introduced their equivalent of a bridge, calling it "LSI" for local silicon interconnect.

TSMC Chiplet.png



from: https://semiwiki.com/semiconductor-...ghts-of-the-tsmc-technology-symposium-part-2/

So, will TSMC customers now refer to their CoWoS-L die as "tiles" rather than chiplets, using the Intel nomenclature? Probably not.
 

Daniel Nenni

Admin
Staff member
You learn something new everyday here on SemiWiki.com:

"Tape-out is the final phase of a design life cycle for a IC design (ASIC/SOC) before the manufacturing starts. (And the same for a PCB design before it is manufactured). This is the phase when the final database that contains the design information is sent to a foundry to begin the manufacturing process. The data base will be in GDSII format. The term tape-out was named so because historically a magnetic tape was used to store all the ASIC design files and this tape was then send to the foundry for manufacturing.

A tape-in is a relatively newer terminology used by certain companies that are involved in bigger SOC (System on Chip) designs that involves integration of several IPs. Some of these organizations will have different groups (and even business units) that work on different IP designs and these are then integrated to a top level SOC design which is finally taped out for manufacturing. When each of the IP groups are ready with their final data base, they tape-in their data base to the top level design team which finally makes a tape-out of full design database to the foundry."

Yes, we were briefed on Intel tiles last week. A detailed article will be out soon. Yes there are some interconnect differences but that does not make it a tile versus a chiplet. Both are marketing terms, and again, one will be an industry standard term and the other will not, just my opinion of course.

The only technical references I have found to "Tape In" are from Intel, the earliest is 2009. Other companies call it IP Integration or IP implementation, not Tape In. For big tiles or chiplets that will be on separate die they will in fact be taped out to test chips. Not a big deal but I'm curious so send me relative links if you have them. Bottom line: Intel tiles and TSMC Chiplets will be taped out not taped in.
 

Portland

Active member
I think they expect the US government to foot the cost of new fabs in the US. They called the $50b the government is planning to spend as a "downpayment". They have pretty much turned into beggers.

$50 billion isn't enough says it all. All our eggs are in a faulty basket.
 
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