The desperate battle for 2 nanometers will heat up next year

[Daniel Nenni]

TSMC's Baoshan plant is expected to install capacity in April and compete with the Kaohsiung plant for mass production in 2025; it will compete with Intel, Samsung, etc.​

It is pointed out that TSMC will accelerate the production of 2nm in April, not only to gain time for advanced process yield ramp-up, but also to continue to pose a threat to Samsung and Intel and open up their lead. Picture/Photo from this newspaper's data

The demand for AI is strong, and there are reports from the semiconductor supply chain that TSMC's Hsinchu Baoshan Fab20 P1 plant will carry out equipment installation work in April to warm up for mass production of the GAA (gate-all-around) architecture. Baoshan P1 and P2 are expected and Kaohsiung's three advanced process wafer fabs will all enter mass production in 2025, and have attracted customers such as Apple, Huida, AMD and Qualcomm to compete for production capacity.

TSMC did not express any opinion on this rumor.

Semiconductor industry players say that whether the wafer manufacturing industry can make a lot of money depends on the yield rate after mass production of the process. The key lies in the yield ramp-up speed. The longer it takes, the higher the cost. Although Samsung claims to be the first to develop the GAA architecture before overtaking in corners, It is said that the yield rate is not good enough to open up the market.

It is pointed out that TSMC's 2nm will accelerate its machine entry in April, not only to gain time for advanced process yield ramp-up, but also to continue to pose a threat to Samsung and Intel and open up their lead. The supply chain revealed that TSMC has prepared for the installation of P1, which is expected to be trial production in the fourth quarter and mass production in the second quarter of next year. Equipment manufacturers pointed out that they have recently deployed manpower and conducted education and training in advance to meet TSMC's customized needs.

As a new milestone in the chip manufacturing process, 2nm will provide higher performance and lower power consumption; adopt nanosheet technology structure, and also develop backside power rail technology. TSMC believes that 2nm will continue TSMC's technology leadership and capture AI growth business opportunities.

The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple.

Different from 3nm, the complex design requires customers to start developing products with TSMC earlier. The market speculates that many customers such as MediaTek, Qualcomm, AMD and Huida have already cooperated; TSMC's press conference also emphasized that the number of N2 customers More than N3 at the same development time.

The competition in 2nm development is fierce. ASML plans to produce 10 2nm EUV lithography machines this year, of which Intel has ordered 6 units. Rapidus Semiconductor Manufacturer, established in Japan with a nationwide effort, is also targeting the 2nm process.

https://www.chinatimes.com/newspapers/20240325000092-260202?utm_source=iii_news&utm_medium=rss&chdtv

 

[Daniel Nenni]

Does anyone know the difference between 3nm and 2nm EUV systems? It is hard to believe that TSMC, ASML's #1 customer, is in line behind Intel.

"The competition in 2nm development is fierce. ASML plans to produce 10 2nm EUV lithography machines this year, of which Intel has ordered 6 units. Rapidus Semiconductor Manufacturer, established in Japan with a nationwide effort, is also targeting the 2nm process."

 

[nghanayem]

Does anyone know the difference between 3nm and 2nm EUV systems?

It's the china times I doubt they have any clue what they are talking about. Considering N2 is almost certainly using the same metal stack and CPP as N3 (or more likely N3E), the only thing they could possibly be talking about (assuming they aren't just totally making things up) is higher throughput models. Which is obviously not node specific.

It is hard to believe that TSMC, ASML's #1 customer is in line behind Intel.

How so? If we take all of this information as true, and for easy math we say ASML makes 10 EUV steppers a year. Okay say TSMC thought they would need 4 steppers this year as they start filling out their HVM sites with tools. Intel buys 3, and the DRAM makers each buy 1. Okay; all well and good. If we now take this rumor as true, and TSMC is pulling in their N2 ramp so they can get down their yield learning curve faster, well okay how? What is ASML (or any tool from any vendor that is sold through for that matter) going to do about it? Tell intel to get bent and that they are diverting their tools to TSMC? No, if TSMC is trying to get extra tool allocation, they will wait in line with everyone else just like how everybody else waits in line at TSMC when they want to go over their wafer agreement. That is how this works.

"The competition in 2nm development is fierce. ASML plans to produce 10 2nm EUV lithography machines this year, of which Intel has ordered 6 units. Rapidus Semiconductor Manufacturer, established in Japan with a nationwide effort, is also targeting the 2nm process."

Maybe they are mixing up high-NA tools? Not that TSMC seems to be using them for N2. If we want to be charitable, maybe TSMC is trying to raise the capacity of their N1.4 pilot line and can't get enough High-NA tools to do so (for the time being anyhow) and the china times can't tell the difference between N2 and N1.4.

The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple.​

I remember back when N5 "wafers cost over double an N7 wafer" and would cost upwards of $20k. I also remember back when N3 wafers "were close to double N5" and costed $45k per wafer. I can't wait for the rumors of N1.4 costing 100k per wafer. Slap on TSMC's margins post ramp, and we got a cool wafer price of $160k.

 

[Daniel Nenni]

I remember back when N5 "wafers cost over double an N7 wafer" and would cost upwards of $20k. I also remember back when N3 wafers "were close to double N5" and costed $45k per wafer. I can't wait for the rumors of N1.4 costing 100k per wafer. Slap on TSMC's margins post ramp, and we got a cool wafer price of $160k.

In the limited history of media covering foundries they NEVER get the wafer or design costs right.

 

[blueone]

In the limited history of mainstream media covering foundries they NEVER get much of anything right.

I fixed that for ya.

 

[hskuo]

Does anyone know the difference between 3nm and 2nm EUV systems? It is hard to believe that TSMC, ASML's #1 customer, is in line behind Intel.

"The competition in 2nm development is fierce. ASML plans to produce 10 2nm EUV lithography machines this year, of which Intel has ordered 6 units. Rapidus Semiconductor Manufacturer, established in Japan with a nationwide effort, is also targeting the 2nm process."

tsmc N3 and N2 use nearly the same design rules, but have transistor architecture change from FinFET to NSFET. There would be no need for Hi NA EUV scanners next year. If Hi NA EUV scanner is necessary for N1.4 which is planned to risk start in 2026/2027, then the HVM tools need to be ready by end of 2025 or 2026 which is the schedule planned by ASML. Will ASML deliver HVM tools on time? From history it seems "will not".
IMO, intel 20A/18A design rule can not match (loose) foundry N3 and definitely no need for Hi NA EUV which has cost 2x higher. Will intel 14A or 10A push the rule more tightly and Hi NA EUV becomes "Must"? I don't know now.

 

[Daniel Nenni]

I do not know how ASML works with customers but I have friends at the local equipment companies and I was told that their relationship with TSMC was close and collaborative while Intel was not close and not collaborative. This may have changed with Pat and the foundry effort but that is why I seriously doubt Intel is getting anything that TSMC is not.

One of the problems with Samsung is the "being first" culture while TSMC is customers first. It looks like Intel is somewhere in the middle, my first impression.

 

[nghanayem]

I do not know how ASML works with customers but I have friends at the local equipment companies and I was told that their relationship with TSMC was close and collaborative while Intel was not close and not collaborative. This may have changed with Pat and the foundry effort

Ann K (and I think even Pat) has mentioned this in some of the previous interviews she has done. Back in the old day intel would say "Hey just drop the tool off at the dock and we will take care of the rest". From there they would cut the vendors out of the loop because A. they didn't want to give competitors any potential insights to accelerate their development via learnings distributed from the vendors, and B. because they thought they were smarter than their vendors . Intel has mentioned a few times that close collaboration with the vendors was now being undertaken to act as a tailwind. The high profile/public examples of this practice in action I can think of is intel pulling to be any early high-NA adopter and the research papers intel co-wrote with AMAT for sculpta's 18A deployment.

https://spie.org/advanced-lithography/presentation/Advancing-EUV-patterning-through-pattern-shaping-at-Intel-18A-process/12958-47?enableBackToBrowse=true#_=_

Are they collaborating with the vendors more than TSMC, I couldn't tell you. But they have clearly come down from the ivory tower.

that is why I seriously doubt Intel is getting anything that TSMC is not.

One of the problems with Samsung is the "being first" culture while TSMC is customers first. It looks like Intel is somewhere in the middle, my first impression.

I mean I don't know what to say other than what I already said. Relationships are irrelevant when it comes to tool deliveries, a vendor will not screw their other customers over because CC batted his eyes and said "pretty please". If intel (or anyone else for that matter) paid for a tool, it is sold, and that is that. Unless said customer cancels or delays their order TSMC has to go to wait for the already contracted units to be delivered first. It is no different than if Apple wanted some extra COWS for some more M3-Ultra volume because demand was exceeding their expectations. I'm sure TSMC would love to sell it, but if they are sold through it is what it is. They won't just shaft NVIDIA out of the capacity they already paid for to make Apple happy. Doing that would ruin TSMC's reputation, lose them business, and get them sued. Same deal applies to a pure-play tool vendor.

 

[hskuo]

I do not know how ASML works with customers but I have friends at the local equipment companies and I was told that their relationship with TSMC was close and collaborative while Intel was not close and not collaborative. This may have changed with Pat and the foundry effort but that is why I seriously doubt Intel is getting anything that TSMC is not.

One of the problems with Samsung is the "being first" culture while TSMC is customers first. It looks like Intel is somewhere in the middle, my first impression.

If checking recent supplier award lists from intel and tsmc, we can find ASML won it from intel but not from tsmc. It tells something.

 

[Fred Chen]

Does anyone know the difference between 3nm and 2nm EUV systems? It is hard to believe that TSMC, ASML's #1 customer, is in line behind Intel.

"The competition in 2nm development is fierce. ASML plans to produce 10 2nm EUV lithography machines this year, of which Intel has ordered 6 units. Rapidus Semiconductor Manufacturer, established in Japan with a nationwide effort, is also targeting the 2nm process."

ASML currently advertises the High-NA EXE 5000 as the "2nm" product https://www.asml.com/en/products/euv-lithography-systems However, only Intel has been enthusiastic about it.

 

[Barnsley]

I fixed that for ya.

Isnt the issue that the media think Semicon starts and ends with ASML & TSMC and nobody else is needed.
I will be generous and say INTEL and NVIDIA are footnotes when media is outside Asia and from US

 

[benb]

chinatimes.com looks like a quality source. I don't know how you find these Dan but keep it up. Being in Mandarin, I clicked translate in Edge and it took care of it pretty well. Zhang Jiarui also seems like a quality journalist.

 

[Scotten Jones]

TSMC's Baoshan plant is expected to install capacity in April and compete with the Kaohsiung plant for mass production in 2025; it will compete with Intel, Samsung, etc.​

It is pointed out that TSMC will accelerate the production of 2nm in April, not only to gain time for advanced process yield ramp-up, but also to continue to pose a threat to Samsung and Intel and open up their lead. Picture/Photo from this newspaper's data

The demand for AI is strong, and there are reports from the semiconductor supply chain that TSMC's Hsinchu Baoshan Fab20 P1 plant will carry out equipment installation work in April to warm up for mass production of the GAA (gate-all-around) architecture. Baoshan P1 and P2 are expected and Kaohsiung's three advanced process wafer fabs will all enter mass production in 2025, and have attracted customers such as Apple, Huida, AMD and Qualcomm to compete for production capacity.

View attachment 1799

TSMC did not express any opinion on this rumor.

Semiconductor industry players say that whether the wafer manufacturing industry can make a lot of money depends on the yield rate after mass production of the process. The key lies in the yield ramp-up speed. The longer it takes, the higher the cost. Although Samsung claims to be the first to develop the GAA architecture before overtaking in corners, It is said that the yield rate is not good enough to open up the market.

It is pointed out that TSMC's 2nm will accelerate its machine entry in April, not only to gain time for advanced process yield ramp-up, but also to continue to pose a threat to Samsung and Intel and open up their lead. The supply chain revealed that TSMC has prepared for the installation of P1, which is expected to be trial production in the fourth quarter and mass production in the second quarter of next year. Equipment manufacturers pointed out that they have recently deployed manpower and conducted education and training in advance to meet TSMC's customized needs.

As a new milestone in the chip manufacturing process, 2nm will provide higher performance and lower power consumption; adopt nanosheet technology structure, and also develop backside power rail technology. TSMC believes that 2nm will continue TSMC's technology leadership and capture AI growth business opportunities.

The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple.

Different from 3nm, the complex design requires customers to start developing products with TSMC earlier. The market speculates that many customers such as MediaTek, Qualcomm, AMD and Huida have already cooperated; TSMC's press conference also emphasized that the number of N2 customers More than N3 at the same development time.

The competition in 2nm development is fierce. ASML plans to produce 10 2nm EUV lithography machines this year, of which Intel has ordered 6 units. Rapidus Semiconductor Manufacturer, established in Japan with a nationwide effort, is also targeting the 2nm process.

https://www.chinatimes.com/newspapers/20240325000092-260202?utm_source=iii_news&utm_medium=rss&chdtv

"The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple."

When 3nm was still in development I had a customer tell me my Strategic Cost and Price Model estimate for 3nm of <$20K was too low and they "heard" the price would be ~$25K. Surprise, 3nm entered production and sold for <$20K. TSMC 2nm is a >1.15x density change, 10-15% performance increase and 25 to 30% lower power, no one is paying $30K for that.

 

[hskuo]

"The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple."

When 3nm was still in development I had a customer tell me my Strategic Cost and Price Model estimate for 3nm of <$20K was too low and they "heard" the price would be ~$25K. Surprise, 3nm entered production and sold for <$20K. TSMC 2nm is a >1.15x density change, 10-15% performance increase and 25 to 30% lower power, no one is paying $30K for that.

Since tsmc N2 using similar DR with N3, the EUV layers should be comparable, but transistor architecture will be changed to NSFET. I would expect price increase less than 30%.
The transistor cost increase ~13%(1.3x/1.15x) for 10-15% performance and 25-30% lower power.

 

[hist78]

If checking recent supplier award lists from intel and tsmc, we can find ASML won it from intel but not from tsmc. It tells something.

That's interesting. ASML is in the TSMC's Outstanding Suppliers list from 2018 to 2022 (I didn't check any pre-2018 data) and missing from the 2023 list.

 

[hskuo]

That's interesting. ASML is in the TSMC's Outstanding Suppliers list from 2018 to 2022 (I didn't check any pre-2018 data) and missing from the 2023 list.

find the hint? intel ordered several Hi NA EUV scanners.........

 

[Fred Chen]

find the hint? intel ordered several Hi NA EUV scanners.........

It might be because the >500 W NXE:3800 https://spie.org/advanced-lithograp...rces-500w-for-high-throughput-in/12953-43#_=_ gives away the earlier source power advantage TSMC had with 400W. However, there's a gotcha regarding the pellicle... https://www.spiedigitallibrary.org/...-wafer-production/10.1117/12.2688127.full#_=_

 

[lefty]

"The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple."

When 3nm was still in development I had a customer tell me my Strategic Cost and Price Model estimate for 3nm of <$20K was too low and they "heard" the price would be ~$25K. Surprise, 3nm entered production and sold for <$20K. TSMC 2nm is a >1.15x density change, 10-15% performance increase and 25 to 30% lower power, no one is paying $30K for that.

I would assume for some one like Nvidia who is buying 10k/month wafers the price per wafer is much lower than a small customer, who is only buying 1000 wafers a month. Maybe $30K is the price quoted to a small customer?

 

[Daniel Nenni]

I would assume for some one like Nvidia who is buying 10k/month wafers the price per wafer is much lower than a small customer, who is only buying 1000 wafers a month. Maybe $30K is the price quoted to a small customer?

I don't think small customers will be using N2 anytime soon unless we see a jump in PPA, they will wait until N2x. N3x has the whole ecosystem in place and will have plenty of capacity once the big customers move to N2. And it won't just be Apple, MediaTek and QCOM will jump on N2. From what I have seen thus far the N2 first customer list will look like N3 as will the roll out, my opinion.

The TSMC Symposium is 3 weeks out. We will know more than. I expect good news! Lots of excitement in the ecosystem, absolutely!

 

[hskuo]

I would assume for some one like Nvidia who is buying 10k/month wafers the price per wafer is much lower than a small customer, who is only buying 1000 wafers a month. Maybe $30K is the price quoted to a small customer?

IMO, economically, there will be no small customer in N2 due to the cost. If the mask set will cost >$20M, and GM is ~50%, wafer price $25k~$30k how much good yield wafers needed to make money? It is not easy for small start-up, unless they have rich daddy.