TechInsights: Introducing TSMC N3E As Seen In Apple M4 SoC

[Fred Chen]

TechInsights Platform

The authoritative information platform to the semiconductor industry.

library.techinsights.com

Introducing TSMC N3E As Seen In Apple M4 SoC | TechInsights

TechInsights shares preliminary results of the Apple M4 analysis on design blocks like GPU and CPU, featuring 2-1 finFLEX and 3-2 finFLEX libraries, respectively. Dive into our on-going analysis and discover the measurements of critical dimensions of TSMC’s 3nm 2nd generation process node: the...

www.techinsights.com

Introducing TSMC N3E: The Power Behind Apple's M4 SoC | TechInsights

In a recent teardown of the Apple iPad Pro 11-inch, TechInsights revealed details of Apple's latest silicon: the Apple M4 SoC, codenamed TMRV93, built on TSMC's advanced N3E process. This surprise release demonstrates Apple's agility in adopting cutting-edge semiconductor technologies ahead of...

www.techinsights.com

I originally had posted the entire introduction article from TechInsights when I could still access it, but now access is removed, so I have to delete essentially all of it. I will just leave the parts which impressed me and are probably not surprising except for the last part.

- N3 utilized spacer-assisted multiple patterning with cut masks on aggressively scaled minimum pitch metal.
- CPP was relaxed for N3E. (As for MMP, something like 28 nm (N5 M0) still counts as "aggressively scaled".)
- TSMC’s N3E process is an evolution from the matured N5/N4 process, without the many innovations deployed by their N3 technology. N3E still provides a design shrink from 4nm and other larger process nodes, supporting products to meet their PPAC objectives.

I was surprised by the statement that N3E retracted many innovations. It seems FinFlex is kept.

 

[Xebec]

Interesting - thanks for sharing!

Am I reading this correct that the M4 die is generally using the UHD library but also using the high performance library for parts of the CPU cores?

Also interesting how the final paragraph reads like N3E is more like N4++ ..

re: why this launched for iPad Pro - two likely reasons, 1. they have a back inventory of Macs they need to sell with older chips, 2. They’re still designing some additional features for the Macs they want to bundle with the M4. From what I can see, the two iPad Pro models (11 and 12.9) combined sell about as many units as total Macs sold per year now. i.e. I don’t think volume of M4 is a real problem here.

 

[Fred Chen]

Interesting - thanks for sharing!

Am I reading this correct that the M4 die is generally using the UHD library but also using the high performance library for parts of the CPU cores?

Yes, that is confirmed in the last link: https://www.techinsights.com/blog/introducing-tsmc-n3e-power-behind-apples-m4-soc:

In a recent teardown of the Apple iPad Pro 11-inch, TechInsights revealed details of Apple's latest silicon: the Apple M4 SoC, codenamed TMRV93, built on TSMC's advanced N3E process. This surprise release demonstrates Apple's agility in adopting cutting-edge semiconductor technologies ahead of schedule.

TSMC's N3E process enhances power efficiency while maintaining logic cell density critical for performance. This aligns well with Apple's goal of delivering high performance in thin devices with passive cooling.

A key design choice in the Apple M4 is the use of TSMC's high-performance standard cell library for CPU1, ensuring optimal power, performance, and cost targets. This contrasts with previous designs relying mainly on ultra-high-density libraries.

TechInsights' analysis also revealed a hybrid library approach: UHD libraries for GPU and CPU2, and a new high-performance library for CPU1. This design optimizes for various computational demands within a unified architecture.

The Apple M4 SoC, leveraging TSMC's N3E process, marks a milestone in mobile computing, setting new standards for performance and efficiency. As Apple continues to innovate, expect further advancements shaping the future of mobile devices.

 

[jorgequinonez]

TechInsights Platform

The authoritative information platform to the semiconductor industry.

library.techinsights.com

Introducing TSMC N3E As Seen In Apple M4 SoC | TechInsights

TechInsights shares preliminary results of the Apple M4 analysis on design blocks like GPU and CPU, featuring 2-1 finFLEX and 3-2 finFLEX libraries, respectively. Dive into our on-going analysis and discover the measurements of critical dimensions of TSMC’s 3nm 2nd generation process node: the...

www.techinsights.com

Introducing TSMC N3E: The Power Behind Apple's M4 SoC | TechInsights

In a recent teardown of the Apple iPad Pro 11-inch, TechInsights revealed details of Apple's latest silicon: the Apple M4 SoC, codenamed TMRV93, built on TSMC's advanced N3E process. This surprise release demonstrates Apple's agility in adopting cutting-edge semiconductor technologies ahead of...

www.techinsights.com

I originally had posted the entire introduction article from TechInsights when I could still access it, but now access is removed, so I have to delete essentially all of it. I will just leave the parts which impressed me and are probably not surprising except for the last part.

- N3 utilized spacer-assisted multiple patterning with cut masks on aggressively scaled minimum pitch metal.
- CPP was relaxed for N3E. As for MMP, something like 28 nm (N5 M0) still counts as "aggressively scaled".
- TSMC’s N3E process is an evolution from the matured N5/N4 process, without the many innovations deployed by their N3 technology. N3E still provides a design shrink from 4nm and other larger process nodes, supporting products to meet their PPAC objectives.

I was surprised by the statement that N3E retracted many innovations. It seems FinFlex is kept.

Thanks for the highlights. Have you tried doing a summary of an article with ChatGPT or Claude for the main points?

 

[Fred Chen]

Thanks for the highlights. Have you tried doing a summary of an article with ChatGPT or Claude for the main points?

I was already trying to avoid excessive disclosure.

 

[chenyj]

Is it ok that someone can comment on the TSMC N3E logic gate length/pitch? There were some public information showing the gate pitch is 45nm (or 42nm), and a simple 0th-order estimation by measuring the "effective channel width" + 18% performance improvement (N3E vs. N5) indicates Lg ~ 16nm. Not sure how close this will be.

 

[nghanayem]

Is it ok that someone can comment on the TSMC N3E logic gate length/pitch? There were some public information showing the gate pitch is 45nm (or 42nm), and a simple 0th-order estimation by measuring the "effective channel width" + 18% performance improvement (N3E vs. N5) indicates Lg ~ 16nm. Not sure how close this will be.

TSMC disclosed 48nm CPP. Lg was not specified.

 

[Fred Chen]

Here is an N3P IP: https://www.dolphin-ic.com/products/standard-cell/tsmc_3p_cell.html

 

[chenyj]

Thanks Fred. TSMC reported 48nm CPP in IEDM, later on I heard of 45nm, and even 42nm (in the article posted here a couple of days ago about TechInsights report on N3E, which disappeared one day later). I was a bit curious and calculated it based on N5 and N3E TEM pictures (2-2 fin cell shown in the article: N3E fin cell height of 173nm which is actually taller than the metal track heigth of 161nm): a 39% density improvement corresponds to a CPP of ~45nm. Lg seems to be a sensitive number, we used to have two sets of data: one value from Manual (typically "6nm") and the real measurement (usually from TechInsights report). And it looks Dolphin Technology also offers two different things: "Channel Lengths 6nm" ..."All tracks available with Channel Lengths 16nm". No clue why people play this kind of thing.

 

[nghanayem]

Thanks Fred. TSMC reported 48nm CPP in IEDM, later on I heard of 45nm, and even 42nm (in the article posted here a couple of days ago about TechInsights report on N3E, which disappeared one day later). I was a bit curious and calculated it based on N5 and N3E TEM pictures (2-2 fin cell shown in the article: N3E fin cell height of 173nm which is actually taller than the metal track heigth of 161nm): a 39% density improvement corresponds to a CPP of ~45nm. Lg seems to be a sensitive number, we used to have two sets of data: one value from Manual (typically "6nm") and the real measurement (usually from TechInsights report). And it looks Dolphin Technology also offers two different things: "Channel Lengths 6nm" ..."All tracks available with Channel Lengths 16nm". No clue why people play this kind of thing.

45pp was for old N3, and I have never seen a 42nm cell for any N3 flavor. Maybe you might have just heard 42nm from some other thing? 6nm channel length doesn't sound possible without TMDs, at least if memory serves from TSMC and intel report outs on their progress on TMDs, that is the Lg regime for 2D/1D channels. 16nm sounds like the actual Lg. Don't know where you got the 173nm number from though. I don't remember the 2 fin having a taller height than the metal stack for the cell (as the cell is as tall is it's tallest component and it just makes sense to relax metal pitch to match since RC improves with no density hit). 48nm and 161nm are consistent with what TSMC quoted (72% the area of N5) (161*48)/(210/51) = 0.722. Don't really know why TSMC is able to get an ARM core area to so nicely match the area of reduction of a std cell when the core has to have SRAM that is barely scaled with respect to N5 and that those core almost certainly sections with lower utilization and dead space where a cell wouldn't fit. But maybe TSMC is only measuring the logic area of the core and that is how they are able to get implementations with density that matches the density uplifts of the std cells themselves.

 

[chenyj]

45pp was for old N3, and I have never seen a 42nm cell for any N3 flavor. Maybe you might have just heard 42nm from some other thing? 6nm channel length doesn't sound possible without TMDs, at least if memory serves from TSMC and intel report outs on their progress on TMDs, that is the Lg regime for 2D/1D channels. 16nm sounds like the actual Lg. Don't know where you got the 173nm number from though. I don't remember the 2 fin having a taller height than the metal stack for the cell (as the cell is as tall is it's tallest component and it just makes sense to relax metal pitch to match since RC improves with no density hit). 48nm and 161nm are consistent with what TSMC quoted (72% the area of N5) (161*48)/(210/51) = 0.722. Don't really know why TSMC is able to get an ARM core area to so nicely match the area of reduction of a std cell when the core has to have SRAM that is barely scaled with respect to N5 and that those core almost certainly sections with lower utilization and dead space where a cell wouldn't fit. But maybe TSMC is only measuring the logic area of the core and that is how they are able to get implementations with density that matches the density uplifts of the std cells themselves.

Metal track and fin cell used to heve the same height, I have the same question why the measured N3E metal track height (161nm) is slightly shorter than 2-2 fin cell height (173nm). Also, assuming the metal track has 5 signal wires, only 2 edge wires show up and the rest of 3 (in the middle) seem to be cut off. I don't have the access to the full TechInsights report, but just manually measured them on a cross-section SEM picture posted here a couple of days ago (withdrawn one day later) . Hopefully, the posted SEM has become public information and won't bring any trouble when shown here again.

 

[Fred Chen]

A potential point of confusion is that TechInsights said the FinFlex was used with N3B not N3E on Apple A17 chip. That's also where the CD images were taken from.