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Tech war: new US restrictions could deny China access to chip making services from TSMC, Samsung

Daniel Nenni

Admin
Staff member
A reported US move to restrict China's access to an advanced semiconductor architecture and high-end memory chips for artificial intelligence (AI) applications could cut it off from access to leading wafer foundries such as Taiwan Semiconductor Manufacturing Co (TSMC) and Samsung Electronics, analysts said.

The Biden administration is considering more restrictions on China's access to a cutting-edge chip architecture known as gate all-around, or GAA, and high bandwidth memory (HBM) AI memory chips, according to a Bloomberg report, citing sources. GAA refers to the next-generation structure of transistors, used in advanced chip manufacturing at the 3-nanometre node and below - levels that Chinese foundries have yet to reach.

Analysts said the potential restrictions could target foreign wafer fabs with GAA capability, making it impossible for them to fabricate chips for China-based clients.

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"It's possible that the US can rally allied countries capable of manufacturing GAA structures not to produce for Chinese chip design firms," said Brady Wang, associate director at research firm Counterpoint.

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The logo of TSMC is seen at southern Taiwan science park in Tainan, Taiwan, December 29, 2022. Photo: Reuters alt=The logo of TSMC is seen at southern Taiwan science park in Tainan, Taiwan, December 29, 2022. Photo: Reuters>

In 2022, Samsung started to use the GAA transistor architecture for the 3-nm process, while (TSMC) - the world's largest contract chip maker - lists a variant of GAA in its technology roadmap for its 2-nm-grade N2 process, according to the company's website.

Washington first restricted China's access to the technology in August 2022, when it prohibited GAA-capable electronic design automation (EDA) software from being exported to countries including China. Last October, the US tightened the net by adding licensing requirements for China-bound shipments of etching and deposition tools required to achieve GAA structures in logic and memory chips.

Despite the restrictions, Chinese firms are studying ways to develop EDA software for GAA transistors, as part of a broader national drive to substitute foreign technologies with domestic solutions even if there are still gaps in performance.

The National Centre of Technology Innovation for EDA - a state-backed research body established last June in Nanjing, capital of eastern Jiangsu province - has added design tools for GAA structures to its technology roadmap, according to a slide shown by the organisation at the Semiconductor World Conference 2024 in Nanjing last week.

Beyond the restrictions on design software, China has also been barred since 2019 from importing extreme ultraviolet (EUV) lithography systems - generally required for manufacturing processes below the 7-nm node. Currently, only three chip makers have used ASML-made EUV systems in mass production: TSMC, Samsung and Intel.

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The Samsung Electronics' Seocho office building in Seoul, South Korea, June 7, 2024. Photo: Bloomberg alt=The Samsung Electronics' Seocho office building in Seoul, South Korea, June 7, 2024. Photo: Bloomberg>

Separately, global demand for HBM chips is on the rise after Nvidia adopted them in its AI architecture to speed up data transfers between graphic processing units and memory stacks.

HBM is on Washington's radar even though there is currently no outright ban in place when it comes to China. However, foreign orders for silicon wafers placed by China and other countries of concern will trigger a red flag alert at entities such as foreign foundries and exporters if the design incorporates more than 50 billion transistors and HBM chips, according to a separate document published by the US Commerce Department in October.

HBM uses 3D stacking, where layers of dynamic random-access memory chips are vertically integrated using technologies such as CoWos, a wafer-level multichip packaging technique invented by TSMC.

"Advanced packaging technology itself has proved quite challenging for the more mature players outside of China," Nicolas Gaudois, UBS head of Asia-Pacific technology research, said during a recent webinar. "You absolutely need to have a leading-edge development process technology as well at the front-end [chipmaking], which China doesn't have."

In a response to questions from the Post, Taiwan-based market research firm TrendForce said China currently does not have the capability to design chips using the GAA architecture, but mainland Chinese packaging and assembly firms like SJ Semiconductor and JCET are capable of doing 2.5D CoWos.

Randy Abrams, head of Taiwan research, at UBS, said it was unclear if the new restrictions would limit chips for consumer smartphones, but as an alternative to GAA, Chinese design houses could use the existing FinFET architecture, which works down to 3-nm, and use larger die sizes for each chip to make up for the performance gap.

 
GAA has many different schemes, I guess the restricted GAA only refers to the two mainstream structures to be used by our global semiconductor industry: GAA Nanosheet (NS) and GAA Forksheet (FS). But does the administration do their job and really think Chinese engineers are not aware of their future risk and not working on something different (or even better) than GAA NS/FS? Even the tri-gate FinFET structure can be easily refined to become a 4-gate or GAA type of FinFET! Look at these new device architectures disclosed in their SPIE paper:

“Mandrel/spacer engineering based patterning and metallization incorporating metal layer division and rigorously self-aligned vias & cuts (SAVC),” Proc. of SPIE, Vol. 12958, 1295802, 2024.
 

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