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Survey papers on managing TLB and designing memories using racetrack memory

sparsh

Member
TLB (translation lookaside buffer) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high-end servers. Since TLB is accessed very frequently and a TLB miss is extremely costly, prudent management of TLB is important.
Domain wall memory (racetrack memory) is a promising emerging memory technology for designing processor components such as cache, register file, shared memory, etc. It offers several attractive features and some challenges.

We present survey papers on both TLB and domain wall memory. PDFs are attached and are also available here.
 
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