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Survey papers on Cache compression, prefetching and power management

sparsh

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With increasing number of on-chip cores, the size of last level cache (LLC) is on rise, e.g., Oracle's 20nm SPARC M7 processor has 64MB LLC, Intel's 22nm Xeon E5-2600 processor has 45MB LLC and IBM's 22nm POWER8 has a 96MB eDRAM LLC. In fact, 70% of the transistors in the Intel Core i3 processor is devoted to caches. Due to these, management of cache has become extremely important.

We present surveys on 1. Compression in cache and main memory 2. Cache Prefetching 3. Dynamic and leakage power management in cache and 4. 'Near-threshold voltage' computing techniques for aggressive power management in caches. These papers may help in getting a bird's eye view of the field of cache management. PDFs are attached and are also available here.
 
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