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We survey architectural techniques for improving the soft-error reliability of PCM (phase change memory) and STT-RAM (spin transfer torque RAM). We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM.
Thanks for your comment. Regarding retention, do you mean "STT-RAM retention failure". Actually, I have not seen many papers on this topic at computer-architectural level of abstraction. So, once there are sufficient number of papers on this topic, a survey can be written